JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A VLSI Design for Digital Pre-distortion with Pipelined CORDIC Processors

  • Park, Jong Kang (School of Electronic and Electrical Eng., Sungkyunkwan Univ.) ;
  • Moon, Jun Young (Dept. of IT Convergence, Sungkyunkwan Univ.) ;
  • Kim, Kyunghoon (Dept. of IT Convergence, Sungkyunkwan Univ.) ;
  • Yang, Youngoo (School of Electronic and Electrical Eng., Sungkyunkwan Univ.) ;
  • Kim, Jong Tae (School of Electronic and Electrical Eng., Sungkyunkwan Univ.)
  • Received : 2014.05.05
  • Accepted : 2014.10.24
  • Published : 2014.12.30
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Abstract

In a wireless communications system, a predistorter is often used to compensate for the nonlinear distortions that result from operating a power amplifier near the saturation region, thereby improving system performance and increasing the spectral efficiency for the communication channels. This paper presents a new VLSI design for the polynomial digital predistorter (DPD). The proposed DPD uses a Coordinate Rotation Digital Computing (CORDIC) processor and a PD process with a fully-pipelined architecture. Due to its simple and regular structure, it can be a competitive design when compared to existing polynomial-type and approximated DPDs. Implementing a fifth-order distorter with the proposed design requires only 43,000 logic gates in a $0.35{\mu}m$ CMOS standard cell library.

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References

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