JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes

  • Kim, Youngmin (School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology (UNIST)) ;
  • Lee, Jaemin (School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology (UNIST)) ;
  • Ryu, Myunghwan (School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology (UNIST))
  • Received : 2014.09.18
  • Accepted : 2014.10.29
  • Published : 2014.12.30
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Abstract

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

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References

  1. International Technology Roadmap for Semiconductors (ITRS), [Online]. Available: http://www.itrs.net/Links/2013ITRS/Home2013.htm
  2. A. B. Kahng, C.-H. Park, X. Xu, and H. Yao, "Layout Decomposition Approaches for Double Patterning Lithography," IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 29, no. 6, pp. 939-952, 2010. https://doi.org/10.1109/TCAD.2010.2048374
  3. K. Yuan, J. S. Yang, and D. Z. Pan, "Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization," IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 29, no. 2, pp. 185-196, 2010. https://doi.org/10.1109/TCAD.2009.2035577
  4. G. Luk-Pat, P. Panaite, K. Lucas, C. Cork, V. Wiaux, S. Verhaegen, and M. Maenhoudt, "Printability Verification for Double-Patterning Technology," in Proc. of SPIE 7122, Photomask Technology, 2008.
  5. C. Cork, J.-C. Madre, and L. Barnes, "Comparison of Triple-Patterning Decomposition Algorithms Using Aperiodic Tiling Patterns," in Proc. of SPIE 7028, Photomask and Next-Generation Lithography Mask Technology XV, vol. 7028, pp. 39.1-7, 2008.
  6. B. Yu, K. Yuan, B. Zhang, D. Ding, and D. Z. Pan, "Layout Decomposition for Triple Patterning Lithography," in Proc. of ICCAD, pp. 1-8, 2011.
  7. Y. Ban, K. Lucas, and D. Pan, "Flexible 2D Layout Decomposition Framework for Spacer-Type Double Patterning Lithography," in Proc. of Design Automation Conference (DAC), pp. 798-794, 2011.
  8. B. Yu, X. Xu, J.-R. Gao, and D. Pan, "Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography," in Proc. of ICCAD, pp. 349-356, 2013.
  9. R. H. Kim, et al., "Double Exposure Using 193nm Negative Tone Photoresist," in Proc. of SPIE Optical Microlithography XX, vol. 65202M, pp. 2M.1-8, 2007.
  10. A. Sezginer, B. Yenikaya, and W. Staud, "Double Patterning Technology: Process-Window Analysis in a Many-Dimensional Space," in Proc. of Photomask and Next-Generation Lithography Mask Technology XIV, vol. 6607, pp. 2S.1-9, 2007.
  11. K. Lucas, et al., "Implications of Triple Patterning for 14nm Node Design and Patterning," in Proc. of SPIE 8327, Design for Manufacturability Through Design-Process Integration VI, vol. 8327, pp. 03.1-12, 2012.
  12. Q. Li, et al., "14nm M1 Triple Patterning," in Proc. of SPIE 8326, Optical Microlithography XXV, vol. 8326, pp. 1-7, 2012.
  13. M. Stucchi, Z. Tokei, S. Demuynck, and Y.-K. Siew, "Impact of Advanced Patterning Options, 193nm and EUV, on Local Interconnect Performance," in Proc. of Interconnect Technology Conference (IITC), 2012 IEEE International, pp. 1-3, 2012.
  14. D. Laidler, et al, "Sources of Overlay Error in Double Patterning Integration Schemes," in Proc. of SPIE Metrology, Inspection, and Process Control for Microlithography XXII, vol. 6922, pp. 1E.1-11, 2008.
  15. K. Jeong, A. B. Kahng, and R. O. Topaloglu, "Is Overlay Error More Important Than Interconnect Variations in Double Patterning?," in Proc. of SLIP, pp. 3-10, 2009.
  16. E. Y. Chin and A. R. Neureuther, "Variability Aware Interconnect Timing Models for Double Patterning," in Proc. of SPIE 7275, Design for Manufacturability Through Design-Process Integration III, vol. 7275, pp. 1-9, 2009.
  17. J.-S. Yang and D. Z. Pan, "Overlay Aware Interconnect and Timing Variation Modeling for Double Patterning Technology," in Proc. Of ICCAD, pp. 488-493, 2008.
  18. R. S. Ghaida and P. Gupta, "Design-Overlay Interactions in Metal Double Patterning," in Proc. of SPIE Design for Manufacturability Through Design-Process Integration III, vol. 7275, pp. 14.1-10, 2009.
  19. T.-B. Chan, K. Jeong, and A. B. Kahng, "Performance and Variability Driven Guidelines for BEOL Layout Decomposition with LELE Double Patterning," in Proc. of SPIE 8166, Photomask Technology, vol. 8166, pp. 30.1-12, 2011.
  20. R. S. Ghaida and P. Gupta, "Within-Layer Overlay Impact for Design in Metal Double Patterning," Semiconductor Manufacturing, IEEE Transactions on, vol. 23, no. 3, pp. 381-390, 2010. https://doi.org/10.1109/TSM.2010.2050157
  21. Raphael reference manual, ver. H-2013.03, [Online]. Available: http://www.synopsys.com.
  22. Hspice reference manual, ver. H-2013.03-SP1, [Online]. Available: http://www.synopsys.com.
  23. 22nm PTM HP models, [Online]. Available: http://ptm.asu.edu.
  24. N. D. Arora, "Modeling and Characterization of Copper Interconnects for SoC Design," in Proc. of International Conference on Simulation of Semiconductor Processes and Devices, pp. 1-6, 2003.
  25. P. Gupta, et al., "Closing the Loop in Interconnect Analyses and Optimization: CMP Fill, Lithography and Timing," in Proc. of International VLSI/ULSI Multilevel Interconnection Conference, pp. 352-363, 2005.
  26. J. Gambino, F. Chen, and J. He, "Copper Interconnect Technology for the 32 nm Node and Beyond," in Proc. of IEEE Custom Integrated Circuits Conference, pp. 141-148, 2009.
  27. D. Sinha, J. Luo, S. Rajagopalan, and S. Batterywala, "Impact of Modern Process Technologies on the Electrical Parameters of Interconnects," in Proc. of International Conference on VLSI Design, pp. 875-880, 2007.