Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Analysis of Nitride traps in MONOS Flash Memory

MONOS 플래시 메모리의 Nitride 트랩 분석

  • Yang, Seung-Dong (Department of Electronics Engineering, Chungnam National University) ;
  • Yun, Ho-Jin (Department of Electronics Engineering, Chungnam National University) ;
  • Kim, Yu-mi (Department of Electronics Engineering, Chungnam National University) ;
  • Kim, Jin-Seob (Department of Electronics Engineering, Chungnam National University) ;
  • Eom, Ki-Yun (Department of Electronics Engineering, Chungnam National University) ;
  • Chea, Seong-Won (Department of Electronics Engineering, Chungnam National University) ;
  • Lee, Hi-Deok (Department of Electronics Engineering, Chungnam National University) ;
  • Lee, Ga-Won (Department of Electronics Engineering, Chungnam National University)
  • Received : 2015.03.19
  • Accepted : 2015.08.03
  • Published : 2015.08.25
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Abstract

This paper discusses the capacitance-voltage method in Metal-Oxide-Nitride-Oxide-Silicon (MONOS) devices to analyzed the characteristics of the top oxide/nitride, nitride/bottom oxide interface trap distribution. In the CV method, nitride trap density can be calculated based on the program characteristics of the nitride thickness variations. By applying this method, silicon rich nitride device found to have a larger trap density than stoichiometric nitride device. This result is consistent with previous studies. If this comparison analysis can be expected to result in improved reliability of the SONOS flash memory.

본 연구에서는 MONOS 플래시 메모리의 blocking oxide/trapping nitride, trapping nitride/tunneling oxide 계면 트랩을 구하기 위해 C-V 방법을 도입하였고, stoichiometric 조건을 만족하는 nitride와 silicon rich nitride를 trapping layer로 갖는 MONOS capacitor를 제작하여 각각의 interface trap 특성을 비교분석하였다. 보고에 따르면 silicon rich nitride는 stoichiometric nitride에 비해 다수의 shallow trap이 존재한다고 보고되고 있는데, 본 연구를 통해 이의 정량화가 가능함을 보였다.

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References

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