The Journal of the Korea institute of electronic communication sciences (한국전자통신학회논문지)

Korea Institute of Electronic Communication Science (한국전자통신학회)
권호 표지
DOI QR코드

DOI QR Code

A Development of Fusion Processor Architecture for Efficient Main Memory Access in CPU-GPU Environment

CPU-GPU환경에서 효율적인 메인메모리 접근을 위한 융합 프로세서 구조 개발

  • Received : 2015.12.22
  • Accepted : 2016.02.24
  • Published : 2016.02.25
Download PDF
⟨ Previous Next ⟩

Abstract

The HSA resolves an old problem with existing CPU and GPU architectures by allowing both units to directly access each other's memory pools via unified virtual memory. In a physically realized system, however, frequent data exchanges between CPU and GPU for a virtual memory block result bottlenecks and coherence request overheads. In this paper, we propose Fusion Processor Architecture for efficient access of main memory from both CPU and GPU. It consists of Job Manager, Re-mapper, and Pre-fetcher to control, organize, and distribute work loads and working areas for GPU cores. These components help on reducing memory exchanges between the two processors and improving overall efficiency by eliminating faulty page table requests. To verify proposed algorithm architectures, we develop an emulator based on QEMU, and compare several architectures such as CUDA(Compute Unified Device Architecture), OpenMP, OpenCL. As a result, Proposed fusion processor architectures show 198% faster than others by removing unnecessary memory copies and cache-miss overheads.

이기종시스템 구조(HSA)는 두 유닛의 각각에 메모리 폴(pools)이 가상메모리를 통해 공유할 수 있게 됨에 따라 CPU와 GPU 아키텍처의 오랜 문제를 해결하였다. 그러나 물리적 실제 시스템에서는 가상메모리 처리를 위해 GPU와 GPU 사이의 빈번한 메모리 이동으로 병목현상(Bottleneck)과 일관성 요청(Coherence request)의 오버헤드를 갖게 된다. 본 연구는 CPU와 GPU간의 효율적인 메인 메모리 접근방안으로 퓨전프로세서 알고리즘을 제안하였다. CPU가 요청한 처리할 메모리 영역을 GPU의 코어에 맞게 분배 제어해주는 기능으로 작업관리자(Job Manager)와 Re-mapper, Pre-fetcher를 제안하였다. 이를 통해 CPU와 GPU간의 빈번한 메시지도 감소되고 CPU의 메모리주소에 없는 Page-Table 요청이 낮아져 두 매체간의 효율성이 증대되었다. 제안한 알고리즘의 검증 방안으로 QEMU(:short for Quick EMUlator)기반의 에뮬레이터를 개발하고 CUDA(:Compute Unified Device. Architecture), OpenMP, OpenCL 등의 알고리즘과 비교평가를 하였다. 성능평가 결과, 본 연구에서 제안한 융합 프로세서 구조를 기존과 비교했을 때 최대 198%이상 빠르게 처리되면서 메모리 복사, 캐시미스 등의 오버헤드를 최소화하였다.

Keywords

References

  1. J. Power, A. Basu, J. Gu, S. Puthoor, B. M. Beckmann, M. Dill, and D. Aood, "Heterogeneous system coherence for integrated CPU-GPU systems," Proceedings of the 46th Annual IEEE/ACM Int. Symposium on Microarchitecture. ACM, California, USA, Dec. 2013. pp. 457-467.
  2. C. Balkesen, J. Teubner, G. Alonso, and M. T. Ozsu, "Main-memory hash joins on multicore CPUs: Tuning to the underlying hardware," Data Engineering (ICDE), 2013 IEEE 29th Int. Conf. on. IEEE, Brisbane, Australia, April 2013. pp. 362-373.
  3. B. Pichai, L. Hsu, and A. Bhattacharjee. "Architectural support for address translation on gpus: Designing memory management units for cpu/gpus with unified address spaces," ACM Special Interest Group on Programming Languages(SIGPLAN) Notices, vol. 49 no.4, 2014, pp 743-758.
  4. G. Kim, M. Lee, J. Jeong, and J. Kim, "Multi-GPU system design with memory networks," Proceedings of the 47th Annual IEEE/ACM Int. Symposium on Microarchitecture. IEEE Computer Society, Cambridge, United Kingdom, Dec. 2014. pp. 484-495
  5. J. Jeffers and J. Reinders, High Performance Parallelism Pearls Volume Two: Multicore and Many-core Programming Approaches, Waltham: Morgan Kaufmann, 2015.
  6. B. Hechtman, A. Blake, and J. Daniel, "Evaluating cache coherent shared virtual memory for heterogeneous multicore chips," Performance Analysis of Systems and Software (ISPASS), 2013 IEEE Int. Symposium on. IEEE, Texas, USA, April. 2013. pp. 118-119.
  7. S. Potluri, H. Wang, D. Bureddy, A. Singh, C. Rosales, and D. Panda, "Optimizing MPI communication on multi-GPU systems using CUDA inter-process communication," Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012 IEEE 26th International. IEEE, Shanghai, China, May 2012. pp. 1848-1857.
  8. S. Lin, Y. Liao, and Y. Hsu, "A Reliable and Secure GPU-Assisted File System," Algorithms and Architectures for Parallel Processing. Springer Int. Publishing, vol. 8630, 2014, pp. 71-84.
  9. I. Singh, A. Shriraman, W. Fung, M. O'Connor, and T. Aamodt, "Cache coherence for GPU architectures," on High Performance Computer Architecture (HPCA), 19th International Symposium on, 2013, pp. 578-590.
  10. S. Kim and Y. Choi, "Analysis of Human Activity Using Motion Vector and GPU," J. of the Korea Institute of Electronic Communication Sciences, vol. 9, no. 10, 2014, pp. 1095-1102. https://doi.org/10.13067/JKIECS.2014.9.10.1095
  11. J. Park, "Comparison Speed of Pedestrian Detection with Parallel Processing Graphic Processor and General Purpose Processor," J. of the Korea Institute of Electronic Communication Sciences, vol. 10, no. 2, 2015, pp. 239-246. https://doi.org/10.13067/JKIECS.2015.10.2.239
  12. S. Lee and W. Jeong, "Design of the Entropy Processor using the Memory Stream Allocation for the Image Processing," J. of the Korea Institute of Electronic Communication Sciences, vol. 7, no. 5, 2012, pp. 1017-1026. https://doi.org/10.13067/JKIECS.2012.7.5.1017