I. INTRODUCTION
Due to the difficulty and cost of replacing the batteries in wireless body area network (WBAN) devices [1], harvesting energy from the environment (ultrasonic [2], thermal [3], vibration [4], solar [5], etc.) to self-power these devices is gradually becoming the most promising solution. Among alternative energy sources in the environment, piezoelectric vibrations are the most attractive since they are steady and have a large power density [6]. An AC to DC converter is required to extract the available power from a piezoelectric transducer in order to power an electronic device.
For instance, the output voltage amplitude range of a piezoelectric transducer generated by human motion can be from tens of millivolts to a thousand millivolts [7]. Therefore, the rectifier in this work should have a low input voltage threshold, a wide input voltage range and a high power conversion efficiency.
Active full-wave rectifiers are widely applied as interface circuits for piezoelectric energy harvesting. Therefore, a MOS switch is driven by a logic circuit which controls the ‘on’ and ‘off’ states according to the voltage difference across the switch itself [8]. The two-stage rectifier presented in [8], which consists of a negative voltage converter (NVC) and an active diode, can achieves about 95% power conversion efficiency (PCE) with input voltages ranging from 1.25 to 3.75 V. Niu D et al. [9] make use of a bulk-driven comparator to improve rectifier sensitivity. This made it possible to achieve an input voltage of 0.28 V and a PCE around 90%. To further reduce the rectifier sensitivity, Yang Z et al. [10] took advantage of an input-powered bulk-driven comparator in the active diode to achieve a rectifier sensitivity of 0.15 V. However, lowering the input voltage amplitude in [9] and [10] is done at the expense of reducing the input voltage range. The input voltage range is 0.28 to 0.7 V in [9] and 0.15 to 0.5 V in [10]. To minimize the switch on-resistance, very large transistors are needed in the NVC, which means a larger die area and cost. In addition, the delay time and offset voltage introduced by the comparator in the active diode [8]-[10] causes a reverse leakage current, which in turn significantly reduces the PCE.
Based on the cross-coupled active full-bridge (CCAF) structure, Lee H M et al. [11] present a novel offset-controlled comparator to minimize the reverse leakage current. The rectifier achieves a PCE equal to 80.5% while operating with an input frequency of 13.56 MHz and an amplitude of 3.8V. Based on the same CCAF structure, Sun Y et al. [12] apply an operational amplifier-controlled active diode and a switch in parallel with a transducer to improve the PCE by solving the dc-offset issue of the comparator-controlled active diode. This rectifier shows a PCE of 90% when operated with a 200 Hz sinusoidal voltage having an amplitude equal to 1.5 V and a resistive load of 95 kΩ. Although the rectifiers in [8], [11], and [12] achieve a higher PCE, the minimum required input voltage amplitude is too high (larger than 1.0 V) to operate the rectifier in a micro-energy environment. The minimum input voltage amplitude is lower in [9] and [10]. This is achieved at the expense of reducing the input voltage range. The vibration energy produced by the human motion is the main energy source for the wearable piezoelectric energy harvester, and the output voltage amplitude is in the range from 0.3 to 1.2 V [7]. Obviously, the above mentioned rectifiers are not suitable for wearable biomedical applications. Moreover, the reported rectifiers provide an output DC voltage that is lower than the maximum input AC amplitude. In [13] the output voltage is insufficient to supply energy to a useful load, especially when the maximum input amplitude is small.
This paper proposes a high efficient full-wave active rectifier based on a single stage Villard doubler with a wide input voltage range. The sensitivity of the rectifier can be as low as 200 mV by employing common-gate comparators with unbalanced bias currents as a part of the active diode, which eliminates the reverse leakage current. The power consumption of the unbalanced-biased comparators (UBCs) can be optimized leading to optimal VCE and PCE. The rest of this paper is organized as follows: section II introduces the basic principle of the Dickson charge pump and comparator-controlled active diode; section III describes the circuit design of the proposed rectifier in detail; simulated and measured results based on the SMIC 0.18-μm standard CMOS process are provided in section IV. Finally, some conclusions are given in section V.
II. BASIC STRUCTURE AND PRINCIPLE
A basic circuit diagram of a one stage Dickson charge-pump rectifier is shown in Fig. 1(a), which consists of diodes D1, D2 and capacitors C1, CS. The forward voltage drop of diodes causes voltage loss in this conduction path, which seriously reduces the VCE and PCE of the rectifier. To cut down voltage drop and improve the performance of the rectifier, the comparator-controlled active diode, as shown in the dashed box in Fig. 1(a), is widely used to replace the passive diode in conventional Dickson charge pump rectifiers. The active diode consists of an NMOS switch and a control comparator [14]. The source and drain of the switch are connected to the non-inverting and inverting input terminals of the comparator, and are equivalent to the cathode and anode terminals of an ideal diode, respectively. The switches operate in the linear region during the on-state and a large size switch is chosen. Therefore, Vd is an extremely low value for the active diode. The output voltage of the charge-pump rectifier can be given as:
Fig. 1.(a) Conventional one-stage Dickson charge pump rectifier and the model of conventional comparator-controlled active diode with non-ideal Delay and offset VOS. (b) The influence of mismatch (I) VOS>0 (II)VOS<0.
However, a signal delay or mismatch of the comparator may lead to a reverse leakage current in the charge pump rectifier, as shown in Fig. 1(a), which can significantly reduce the efficiency of rectifier [11], [12]. In Fig. 1(a), the delay represents the signal delay of the comparator COMP which is mainly caused by the parasitic capacitance of the large size switch MS. In addition, VOS is an offset voltage induced by random errors in the process.
Due to the requirements of a large output power and a small voltage drop, a large-size switch transistor MS should be chosen. Therefore, the parasitical gate-capacitance of MS increases unavoidably. As a result, the time for charging or discharging this capacitance will be increased correspondingly.
Offset voltage VOS is caused by a mismatch or another random error in the process [15]. As shown in Fig. 1(b), the output of an ideal comparator is illustrated as a dotted line, which turns the NMOS switch MS on once VS lower than GND (t2 or t5) and turns it off immediately when VS is higher than GND (t3 or t8). When VOS=VS(t1)-VS(t2)=VS(t4)-VS(t3)>0, as shown in Fig. 1(b)(I), MS is turned on at t1 and turned off at t4, for the effect of VOS, instead of t2 and t3. Although VS is higher than GND during the phase of t1-t2, switch MS is still turned on and the conduction path is formed for the reverse current ISD from the drain to the source of MS. Similarly, when VOS=VS(t6)-VS(t5)=VS(t7)-VS(t8)<0, as shown in Fig. 1 (b)(II), MS is turned on at t6 and turned off at t7, instead of t5 and t8. However, in this case, the negative offset voltage VOS does not lead the reverse current through the switch MS. Instead it makes the voltage drop across it increase. Therefore, when the offset voltage of the comparator VOS>0, the terrible influences of the signal delay VDelay will be superimposed with the effects of the offset voltage VOS, which is the worst case in many applications. However, if VOS<0, the influences of VDelay can be cancelled out by the offset voltage VOS. Generally, the equivalent offset voltage VDelay is larger than the voltage VOS especially for a high input frequency [12]. Therefore, even if the offset voltage VOS<0 is taken into consideration, the signal delay of the comparator Delay still causes the reverse leakage problem, which decreases the efficiency of the rectifier.
In this paper, a built-in offset voltage ΔV is introduced into the comparator by the unbalanced bias schematic to compensate VDelay and VOS. Considering the worst case, in order to prevent a reverse leakage current as much as possible, the built-in offset voltage ΔV should be chosen appropriately and is set as |ΔV|≥|VDelay|+|VOS| in this design. If the built-in offset voltage ΔV over compensates the reverse leakage, the voltage drop across MS increases and the VCE of the rectifier decreases correspondingly. However, a large MS is designed to meet the requirements of a large output power and a small voltage drop. Once the reverse leakage conduction path is formed, there will be a large reverse current distracting the energy stored in the capacitor CS, which lead to drastic reductions in the PCE. Therefore, the performance of the PCE has been paid more attention to in this design example.
III. PROPOSED ACTIVE VOLTAGE-DOUBLING RECTIFIER
Efficiency is one of the most important performance indicators for a rectifier, and it is influenced by three factors: 1) the power consumption dissipated by the on-resistance of the MOSFET switch in an active diode; 2) the power consumption dissipated by the active part of a rectifier (comparators and their bias circuits); 3) the power loss caused by the reverse leakage current mentioned in section II. In addition, the input voltage range of a rectifier should be as wide as possible to harvest more vibration energy with different amplitudes. Taking these factors into consideration, a high efficiency, wide input range active voltage doubling rectifier with unbalanced-biased comparators is proposed in this paper.
A. The Proposed Active Voltage Doubling Rectifier
A schematic of the proposed active voltage doubling rectifier is shown in Fig. 2. The main schematic topology of the proposed active rectifier is based on an approach first presented in [16]. The proposed rectifier mainly consists of five parts: unbalanced-biased comparators (UBCs) COMP1 and COMP2, power transistors MS1 and MS2, bypass transistors MB1 and MB2, off-chip capacitors C1 and CS, and a bulk regulation circuit. The NMOS MS1 and the comparator COMP1 constitute the active diode D1, and the PMOS MS2 and the comparator COMP2 constitute the active diode D2. Both MS1 and MS2 operate in the linear region. Therefore, increasing the size of MS1 and MS2 leads to smaller on-resistances of the switches and a drain-source voltage drop, thereby maximizing the voltage conversion efficiency. ΔV1 and ΔV2 are the built-in offset voltages of the UBCs, which are generated by the unbalanced bias currents ISN1, ISN2 and ISP1, ISP2, respectively. As previous analysis, a build-in offset voltage can prevent the reverse current induced by the random offset and delay of the comparator. To reduce the power consumption dissipated by the active part of the rectifier, the common-gate comparators COMP1 and COMP2 are biased in the subthreshold regions. As a result, they only dissipate several hundred nano-amperes of current. The proposed UBCs enable the rectifier to operate with a low amplitude input and minimize the leakage current to improve the rectifier efficiency by compensating the delay and mismatch.
Fig. 2.Proposed active voltage doubling rectifier with UBCs.
To reduce the on-state resistor, the power transistors MS1 and MS2 should always have a large size. In this rectifier, two bypass diodes MB1 and MB2 are added in parallel with the switches MS1 and MS2, to promote the start-up performance especially in very low input voltage conditions. The bulk regulation circuit aims at preventing the forward bias between the source and body of MS2, which may cause a latch-up. C1 is a sampling capacitor, and the holding capacitor CS stores the scavenged piezoelectric energy and delivers power to the rectifier and the load.
B. Design of the Unbalanced-biased Comparator
As analyzed in section II, the mismatch and delay of the comparators can cause performance degeneration of the rectifier. In this paper, an unbalanced-biased approach is adopted in the comparator design to form a built-in voltage difference ΔV [17]-[19] and then to compensate the non-ideal effects of the comparator. Fig. 3 shows a detailed circuit diagram of the proposed unbalanced-biased comparators. Due to the level of their input voltage ranges, COMP1 and COMP2 are symmetrical, and have to be supply compatible and ground compatible. Taking COMP1 for example, the comparator consists of two pairs of common gate input stages (M1, M5 and M2, M6), a current mirror (M3, M4), a common source inverter (M7, M8), and a push-pull inverter (M9, M10). COMP1 and COMP2 are supplied by the output of the rectifier itself. Additionally, a positive feedback loop formed by the capacitor C can prevent the comparator from oscillating. Simulation results indicate that the value of the capacitor C can be set as 0.2pF and the resistor R can be set as 0.5MΩ.
Fig. 3.Circuits of the UBC COMP1 with NMOS input and COMP2 with PMOS input.
As shown in Fig. 3, ISN1 and ISN2 are unbalanced current sources, which are mirrored by M5 and M6 to generate the unbalanced bias for M1 and M2. By setting the biasing current to ISN1≠ISN2, the value of ΔV in the proposed unbalanced-biased comparator can be properly controlled by the difference between ISN1 and ISN2. For the power consumption consideration, M1 and M2 are biased in the subthreshold, and the subthreshold current is expressed as:
Where K is W/L of the MOS transistor, I0=μCOX(η-1)VT2, η is a non-ideal factor which is estimated as a constant parameter equal to 1.14 and 1.40 for the PMOSFET and NMOSFET, respectively [20]. The subthreshold currents ISN1 and ISN2 flowing through M1 and M2 can be expressed as:
The ΔV of COMP1 can be obtained from (3).
As can be seen from (4), the built-in voltage difference mainly depends on the ratio of ISN1/ISN2. Take ISN1/ISN2=3/4, by setting the bias circuit properly (discussed in the following section), VT=26mV and η=1.4 for the NMOS transistor. A negative offset voltage ΔV1≈-10.5mV is obtained.
The source terminals of the input MOSFET M1 and bias MOSFET M6 are connected as the inverted input terminal of COMP1, and those of M2 and M5 are connected at the non-inverted input terminal. This structure realizes the push-pull output in the first stage of COMP1, and then minimizes the delay time of the comparator [22]. Two inverters (M7, M8 and M9, M10) are used to increase the output swing and to improve the driving capability of COMP1. The common gate structure is adopted as the input stage of COMP1 to meet the low voltage input demand.
COMP1 and COMP2 are symmetrical. Therefore, in a similar way, by setting the biasing current to ISP1≠ISP2, the built-in offset voltage ΔV2 of COMP2 can be expressed as (5). Take ISP2/ISP1=4/3, VT=26mV and η=1.14 for the PMOS transistor. A positive offset voltage ΔV2≈8.5mV is obtained.
It is impossible for the built-in offset voltage ΔV to completely cancel the non-ideal effect, due to the randomness of the mismatch. However, a slightly larger ΔV is appropriate to minimize the reverse leakage current which is caused by the mismatch and delay of the comparator. It is worth mentioning that an excessive ΔV may lead to a voltage-drop increase of the active switch in the on-state, which can result in a performance degradation of the rectifier.
As shown in section III. A, the proposed rectifier is supplied by an output voltage, which varies widely in the start-up phase due to the wide input voltage range. In order to ensure the accuracy of the built-in offset voltage ΔV, the unbalanced bias currents of the comparators should be independent from the supply voltage. On the other hand, since the proposed rectifier is powered only by harvested energy, its own power dissipation should be as low as possible to deliver more energy to the load. Therefore, the bias circuits should keep the current consumption constant as the supply voltage increases. The proposed supply independent, unbalanced bias circuit is shown in Fig. 4. M21-M23 operating in the subthreshold constitute the current mirrors. Therefore, the currents flowing through M24 and M25 are the same.
The current flowing through resistor R is:
Fig. 4Supply independent unbalanced current source.
As shown in (7), this current only depends on the W/L ratio of M24 and M25 and the resistance of R. It can also be seen that it is independent of the supply voltage. By setting different W/L ratios of M27 and M28, the unbalanced bias currents ISN1 and ISN2 are generated, which are used to bias COMP1. Similarly, the unbalanced bias currents of COMP2 ISP1 and ISP2 can be obtained by setting different W/L ratios of M29 and M30. As shown in (5), the built-in offset voltage of the comparator can be adjusted by changing the W/L ratio of the MOSFETs in the bias circuit. Since the leakage of the body-drain diode was exploited to inject a current into nodes A and B, two dummy MOSFETs ML1 and ML2, as shown in Fig. 4, are used to aid the start-up.
C. Bypass Diode and Bulk Regulate Circuit
Under some worst-case conditions, such as process variations with a high threshold and a low operating temperature, the comparator-based active diode may not work properly, especially in the start-up phase. In order to assure a safe and robust start-up of the active diode, two additional bypass MOS diodes (MB1 and MB2) in parallel with the active diodes (MS1 and MS2) can be used. The bypass MOS diodes ensure that there is a startup-aid current flowing through it, and minimize the setting time of the rectifier. After the active diode starts working, MB1 and MB2 are no longer operating and are always keep in a high impedance state, which guarantees that there is no reverse leakage current through the bypass diode. To insure a large drain current in a weak positive biased condition, the W/L ratio of MB1 and MB2 should be relatively large.
In CMOS technologies, the slightly p-doped bulk must always be connected to the lowest potential, and the n-doped well of a PMOS transistor must be connected to the highest potential. Then, the PN junctions are reversed biased and no leakage current or latch-up occurs. However, during the start-up phase, the source and drain of the PMOS MS2 are floating and alternating, which makes it unclear how to connect its substrate. In consideration of performance, a dynamic bulk regulation circuit is added to make sure that the bulk of the PMOS MS2 is always connected to the highest potential between VS and Vout. The W/L ratio of the switch MP1 (and MP2) is small. Therefore, it can be directly controlled by the output of the comparator.
IV. RESULTS AND DISCUSSIONS
The proposed wide input range active voltage doubling rectifier is implemented and simulated with the SMIC 0.18μm standard CMOS process. Table I shows the size of all of the transistors in the proposed rectifier. The integral layout of the proposed rectifier is shown in Fig. 5(a), and Fig. 5(b) presents more layout details of the core circuit. The area cost of the whole rectifier chip and the core circuit are 0.91×0.97mm2 and 0.31×0.37mm2, respectively. All of the main switches are surrounded by guard rings to isolate them from adjacent cells. Pads with electro-static discharge (ESD) protection are used to feed the input source signal into the chip. The ESD supply voltages (VDD and VSS) are directly accessible. The parasitic parameters of the rectifier are extracted to simulate the post-layout for more accurate results. In addition, some measurement results are given in the following part of this section as well.
TABLE ISIZE OF ALL TRANSISTORS IN THE PROPOSED RECTIFIER
Fig. 5.(a) Integral layout of proposed rectifier. (b) Core circuit layout of proposed rectifier.
To verify the performance of the proposed active voltage doubling rectifier, the PCB Demo board is designed as shown in Fig. 6(a). A sinusoidal signal generator is connected to the input of the proposed rectifier, and the output is connected to an oscilloscope. The experimental platform is shown in Fig.6(b).
Fig. 6.(a) The PE harvester Demo. (b) The experimental platform.
Fig. 7(a) shows the waveforms of the output voltage under different input signal amplitudes with an input AC frequency of 200Hz. The range of the input amplitude can be from 0.2V to 1.0V, and the corresponding stable output DC voltage range is about 0.4 to 2.0V, which is double that of the input voltage amplitude. The minimum input amplitude is as low as 0.2V. However, the setup time becomes as long as 12.5s under this condition. Fig. 7(b) demonstrates the effects of different input frequencies and amplitudes on the voltage conversion efficiencies of the rectifier with a 100kΩ load. As shown in Fig. 7(b), when the amplitude of the input signal is 0.2V, the switch transistors MS1 and MS2 operates in the subthreshold region. Therefore, the on-resistance of these switches increases, which causes a significant decrease in the VCE. In addition, when the amplitude of the input signal is 0.6 or 1.0V, the two switch transistors operate in the linear region, and the measured results of the VCE are above 95% with the frequency of the input signal ranging from 20 to 3000Hz. In addition, as can be seen from Fig. 7(b), the VCE decreases slightly with an increase of the input signal frequency. This is based on the fact that the impact of the delay on the switches is worse when the signal cycle becomes smaller. The measured output voltage Vout, VS of the proposed rectifier and the input AC signal Vin at different frequency are shown in Fig. 7(c) and 7(d), respectively. With | Vin |=0.2V and a 20kΩ load resistance, the proposed rectifier provides a Vout of about 0.374V at a frequency of 200Hz and 1.92V at a frequency of 3kHz, respectively.
Fig. 7.(a) Output voltage with different input signal amplitudes (b) VCE versus input signal frequency. Measured voltages of the proposed rectifier with (c) Vin=0.2V@200Hz. (d) Vin=1.0V@3kHz.
Fig. 8(a) and 8(b) presents the simulation results of 500 Monte Carlo iterations of the two proposed comparators with the unbalanced biasing scheme. As shown in Fig. 8(a), the mean value (μ) of the offset voltage is -8.07mV, with a standard deviation (σ) of 1.79mV for the proposed comparator COMP1. These two parameter values are 6.76mV and 1.66mV for the comparator COMP2, as shown in Fig. 8 (b). Even with a 3σ variation (99.7%), the possible spread of the offset voltages in two comparators is sufficiently small. Therefore, the build-in offset voltage ΔV does not change its sign. As mentioned in section II, the correct sign of the voltage ΔV can effectively reduce the reverse leakage current, and then improve the PCE of the proposed rectifier.
Fig. 8.Monte Carlo simulation of the offset voltages of the comparators with UBS. (a) COMP1. (b) COMP2.
As shown in Fig. 9(a), a rectifier without unbalanced biased comparators presents a reverse leakage in both the negative and positive half circle of the input signal. As a result, this reverse leakage current problem severely degrades the conversion efficiency of the rectifier. Fig. 9(b) presents a waveform of the proposed rectifier with unbalanced biased comparators. As can be seen in Fig.9(b), the switches MS1 and MS2 are turned off opportunely, and there is seldom a reverse leakage current. The output of COMP1, COMP2 and the voltage of VS are measured and shown in Fig.9(c) with | Vin |=0.6V at a frequency of 200Hz. It can be seen from the output voltage waveforms of COMP1 and COMP2 that the two comparators turn off timely to reduce the reverse leakage current. As a single stage Dickson charge pump rectifier, the VCE of the proposed rectifier is given by:
Fig. 9.(a) Post-simulated waveforms of the reverse leakage current in Common rectifier without UBCs. (b) Post simulated waveforms of the reverse leakage current in proposed rectifier with UBCs. (c) Measured voltages of proposed rectifier with UBCs.
Where Vout is the stable output DC voltage, and Vp is the amplitude of the input signal. The PCE of the rectifier is given by (9), where Pload is the output power consumed on the load resistor RL, Pactive is the power dissipated by the active parts of the rectifier (comparators and bias circuit), and Ploss is the total loss power dominated mainly by the Ron loss of the switches.
Fig. 10(a) and 10(b) show the effect of the unbalanced biased comparators on the power conversion efficiency and voltage conversion efficiency of rectifiers with different loads. As a typical description, the input source is set as a sinusoidal signal at a frequency of 1000Hz. As can be seen from Fig. 10(a), the measured peak PCE of the proposed rectifier reaches 92.5% with an input amplitude of 0.6V and a load resistance of 20kΩ. For two different load conditions and input amplitudes ranging from 0.2 to 1.0V, when compared with the simulated results of a rectifier without the UBCs, the measured PCE of the proposed rectifier in improved by 12%-14%. With the load resistance increasing, the power consumption on the load of P load decreases, and the PCE of the rectifier decreases as illustrated in (9). It is worth noting that the switches MS1 and MS2 operate in the subthreshold region when the input voltage amplitude is less than 0.3V. This causes the on-resistance of these switches to increase and the conversion efficiency to decrease. As shown in Fig. 10(b), the measured average VCE of proposed rectifier is higher than 95% when the input amplitude is greater than 0.3V and the load resistance is larger than 20kΩ. When compared with the simulated VCE of a rectifier without the UBCs, the VCE of the proposed rectifier decreases by about 1%-2%. To prevent the reverse leakage current as much as possible, the built-in compensate voltage ΔV should be set large than |VDelay|+|VOS| as mentioned in section III. B. Therefore, the voltage ΔV may be overcompensation for the non-ideal effect. An excessive ΔV can lead to a voltage-drop of the active switch increase in the on-state. This in turn result in VCE performance degradation of the rectifier. Compared with the obvious improvement of the PCE, the slight performance degradation in the VCE can be neglected.
Fig. 10.Simulated and measured. (a) PCE. (b) VCE versus the amplitude of input signal with different loads.
Table II presents the performance of the proposed rectifier and a comparison with previously published state-of-the-art works. The proposed rectifier exhibits excellent performance in terms of power conversion efficiency and a wide input amplitude range. It also achieves the output voltage double. The proposed rectifier can source a 100μA output current into a 20kΩ load resistance, operate at a 200mV input amplitude, and achieve the highest voltage conversion ratio and power efficiency when compared to its counterparts. Therefore, the proposed rectifier is suitable for power transmission systems with a wide input range and a high current output for improving system power efficiency.
TABLE IIPERFORMANCE AND COMPARISON WITH PRIOR ART
V. CONCLUSIONS
In this paper, a highly efficient integrated active voltage doubling rectifier is proposed with a wide input range for piezoelectric energy harvesting systems. The voltage drop along the conduction path is minimized by replacing the passive diode with a comparator-controlled active diode. By using the charge pump topology, the output of the proposed rectifier can boost the input signal amplitude. The common-gate input comparators biased in the subthreshold region effectively reduce the minimum start up voltage of the proposed rectifier. The built-in offset voltages in the comparators implemented by the unbalanced biases suppress the reverse leakage current caused by the delay and process deviations, and improve the efficiency performances of the rectifier. In addition, two bypass MOS diodes and a bulk regulating circuit are added in the proposed rectifier to achieve a safe and robust start-up. The proposed rectifier is simulated and implemented with the SMIC 0.18-μm standard CMOS process. The measured results show that proposed rectifier achieves favorable performances in terms of the input voltage range and conversion efficiency. The proposed rectifier is very suitable for harvesting ultralow piezoelectric energy for portable and wearable electronic biomedical applications.
References
- F. Xu, G. Yan, K. Zhao, L. Lu, and G. Liu, “A wireless capsule system with asic for monitoring the physiological signals of the human gastrointestinal tract,” IEEE Trans. Biomed. Circuits Syst., Vol. 8, No. 6, pp. 871-880, Dec. 2014. https://doi.org/10.1109/TBCAS.2013.2296933
- F. Mazzilli, C. Lafon, and C. Dehollain, “A 10.5 cm ultrasound link for deep implanted medical devices,” IEEE Trans. Biomed. Circuits Syst., Vol. 8, No. 5, pp. 738-750, Oct. 2014. https://doi.org/10.1109/TBCAS.2013.2295403
- Y. K. The and P. K. T. Mok, “Design of transformer-based boost converter for high internal resistance energy harvesting sources with 21 mV self-startup voltage and 74% power efficiency,” IEEE J. Solid-State Circuits, Vol. 49, No. 11, pp. 2694-2704, Nov. 2014. https://doi.org/10.1109/JSSC.2014.2354645
- T. Hehn, F. Hagedorn, D. Maurath, D. Marinkovic I. Kuehne, A. Frey, and Y. Manoli, “A fully autonomous integrated interface circuit for piezoelectric harvesters,” IEEE J. Solid-State Circuits, Vol. 47, No. 9, pp. 2185-2198, Sep. 2012. https://doi.org/10.1109/JSSC.2012.2200530
- M. Kasemann, J. Kokertm S. M. Torres, K. Rühle, and L. M. Reindl, "Monitoring of indoor light conditions for photovoltaic energy harvesting," in Proc. Multi-Conference on Systems, Signals & Devices (SSD), pp. 1-5, 2014.
- S. J. Roundy, "Energy scavenging for wireless sensor nodes with a focus on vibration to electricity conversion," Ph.D. Dissertation, University of California, Berkeley, USA, 2003.
- Y. Minami and E. Nakamachi, "Development of enhanced piezoelectric energy harvester induced by human motion," IEEE Engineering in Medicine and Biology Society Annual Conference, pp. 1627-1630, 2012.
- Peters C, Spreemann D, Ortmanns M, et al. “A CMOS integrated voltage and power efficient AC/DC converter for energy harvesting applications,” Journal of Micromechanics and Micro Engineering, Vol. 18, No. 10, pp. 1589-1604, Sep.. 2008.
- D. Niu, Z. Huang, M. Jiang, and Y. Inoue, “A sub-0.3 V highly efficient CMOS rectifier for energy harvesting applications,” IEICE Nonlinear Theory and Its Applications, Vol. 3, No. 3, pp. 405-416, Sep. 2012. https://doi.org/10.1587/nolta.3.405
- Z. Yang, Y. Li, J. Wang, Z. Zhu, and Y. Yang, “A highly efficient interface circuit for ultra-low-voltage energy harvesting,” IEICE Electronics Express, Vol. 10, No. 24, pp. 20130869, Dec. 2013. https://doi.org/10.1587/elex.10.20130869
- H. M. Lee and M. Ghovanloo, “An integrated power-efficient active rectifier with offset-controlled high speed comparators for inductively powered applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 58, No. 8, pp. 1749-1760, Aug. 2011. https://doi.org/10.1109/TCSI.2010.2103172
- Y. Sun, N. H. Hieu, C. J. Jeong, and S. G. Lee, “An integrated high-performance active rectifier for piezoelectric vibration energy harvesting systems,” IEEE Trans. Power Electron., Vol. 27, No. 2, pp.623-627, Feb. 2012. https://doi.org/10.1109/TPEL.2011.2162078
- S. Cheng, R. Sathe, R. D. Natarajan, and D. P. Arnold, “A voltage-multiplying self-powered AC/DC converter with 0.35-V minimum input voltage for energy harvesting applications,” IEEE Trans. Power Electron., Vol. 26, No. 9, pp. 2542-2549, Sep. 2011. https://doi.org/10.1109/TPEL.2011.2109969
- L. Karthikeyan and B. Amrutur, “Signal-powered low-drop-diode equivalent circuit for full-wave bridge rectifier,” IEEE Trans. Power Electron,, Vol. 27, No. 10, pp. 4192-4201, Oct. 2012. https://doi.org/10.1109/TPEL.2012.2190828
- Q. Li, Z. Huang, R. Zhang, M. Jiang, B. Lin, and Y. Inoue, “A low voltage CMOS rectifier for low power battery-less devices,” IEICE Nonlinear Theory and Its Applications, Vol. 1, No. 1, pp.186-195, Jan. 2010. https://doi.org/10.1587/nolta.1.186
- E. Dallago, G. Frattini, D. Miatton, G. Ricotti, and G. Venchi, "Self-supplied integrable high efficiency AC-DC converter for piezoelectric energy scavenging systems," in Proc. IEEE ISCAS, pp. 1633-1636, 2007.
- S. Guo and H. Lee, “An efficiency-enhanced CMOS rectifier with unbalanced-biased comparators for transcutaneous powered high-current implants,” IEEE J. Solid-State Circuits, Vol. 44, No. 6, pp.1796-1804, Jun. 2009. https://doi.org/10.1109/JSSC.2009.2020195
- H. M. Lee and M. Ghovanloo, “An integrated power-efficient active rectifier with offset-controlled high speed comparators for inductively powered applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 58, No. 8, pp. 1749-1760, Aug. 2011. https://doi.org/10.1109/TCSI.2010.2103172
- E. Dallago, D. Miatton, G. Venchi, V. Bottarel, G. Frattini, G. Ricotti, and M. Schipani, "Active autonomous AC-DC converter for piezoelectric energy scavenging systems," in Proc IEEE CICC, pp.555-558, 2008.
- Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, 2nd ed., Cambridge University Press, Chap. 3, 2009.
- C. Peters, J. Handwerker, D. Maurath, and Y. Manoli, "An ultra-low-voltage active rectifier for energy harvesting applications," in Proc. IEEE ISCAS, pp. 889-892, 2010.
- F. Tahami, S. Poshtkouhi, and H. M. Ahmadian, “Piecewise affine control design for power factor correction rectifiers,” Journal of Power Electronics, Vol. 11, No. 3, pp. 327-334, May 2011. https://doi.org/10.6113/JPE.2011.11.3.327
Cited by
- Battery voltage-balancing applications of disk-type radial mode Pb(Zr ∙ Ti)O3 ceramic resonator vol.56, pp.10S, 2017, https://doi.org/10.7567/JJAP.56.10PD03
- A Self-Powered Piezoelectric Energy Harvesting Interface with Wide Input Range in 65 nm CMOS Process pp.0974-780X, 2017, https://doi.org/10.1080/03772063.2017.1375439
- A self-powered zero-quiescent-current active rectifier for piezoelectric energy harvesting vol.15, pp.18, 2018, https://doi.org/10.1587/elex.15.20180739