전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제53권8호
  • /
  • Pages.39-48
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  • 2016
  • /
  • 2287-5026(pISSN)
  • /
  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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멀티 핀/핑거 FinFET 트랜지스터의 열 저항 해석과 모델링

Analysis and modeling of thermal resistance of multi fin/finger FinFETs

  • 장문용 (성균관대학교 정보통신대학) ;
  • 김소영 (성균관대학교 정보통신대학)
  • Jang, MoonYong (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, SoYoung (College of Information and Communication Engineering, Sungkyunkwan University)
  • 투고 : 2016.05.28
  • 심사 : 2016.07.28
  • 발행 : 2016.08.25
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초록

본 논문에서는 소스와 드레인의 구조가 육각형인 FinFET에서 구조 변수 및 핀/핑거 개수 증가에 따른 열 저항 모델을 제안한다. 소자의 크기가 감소하여 발열 효과 및 열 특성의 영향이 커졌으며, 이를 분석하기 위해 소자의 열 저항은 중요한 요소이다. 열 저항 모델은 소자에서 열이 생성되는 열원과 열이 빠져나가는 contact를 설정했으며, 도메인은 열원과 4 부분의 소스, 드레인, 게이트, 서브스트레이트 contact를 통해 나누어진다. 또 각각의 contact 열 저항 모델은 TCAD의 시뮬레이션 결과의 온도 및 열 흐름을 분석하여 해석이 용이한 형태로 세분화하였다. 도메인들은 그 구조에 따라 구조 변수를 통한 적분 및 등각 매핑 방식을 기반으로 모델링하였다. 먼저 싱글 핀으로 열 저항을 분석하여 모델링하였으며, 멀티 핀/핑거의 열 저항 모델의 정확도를 높이기 위해 채널증가에 따른 파라미터의 변화를 적용하였다. 제안한 열 저항 모델은 3D Technology CAD 시뮬레이션을 해석하여 얻은 열 저항 결과와 비교하였으며, 싱글 핀 및 멀티 핀의 전체 열 저항 모델은 3 % 이하의 오차를 얻었다. 제안한 열 저항은 핀/핑거 개수의 증가에 따른 열 저항을 예측할 수 있으며, 발열효과 및 열 특성 분석을 계산하여 회로 특성을 개선할 수 있다.

In this paper, we propose thermal resistance compact model of FinFET structure that has hexagon shaped source/drain. The heating effect and thermal properties were increased by reduced size of the device, and thermal resistance is an important factor to analyze the effect and the properties. The heat source and each contact that is moved heat out were set up in transistor, and domain is divided by the heat source and the four parts of contacts : source, drain, gate, substrate. Each contact thermal resistance model is subdivided as a easily interpretable structure by analyzing the temperature and heat flow of the TCAD simulation results. The domains are modeled based on an integration or conformal mapping method through the structure parameters according to its structure. First modeled by analyzing the thermal resistance to a single fin, and applying the change in the parameter of the channel increases to improve the accuracy of the thermal resistance model of the multi-fin/ finger. The proposed thermal resistance model was compared to the thermal resistance by analyzing results of the 3D Technology CAD simulations, and the proposed total thermal resistance model has an error of 3 % less in single and multi-finl. The proposed thermal resistance model can predict the thermal resistance due to the increase of the fin / finger, and the circuit characteristics can be improved by calculating the self-heating effect and thermal characterization.

키워드

참고문헌

  1. C. Auth et al., "A 22nm High Performance and Low Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistor, Self-Aligned Contacts and High Density MIM Capacitors", Symposium on VLSI Technology, pp. 131-132, June. 2012.
  2. K. K, Choe, K. W Kwon, S. Y. Kim, "Circuit Performance Prediction of Scaled FinFET Following ITRS Roadmap based on Accurate Parasitic Compact Model", The Institute of Electronics Engineers of Korea, vol 52, pp. 33-46, Oct. 2015.
  3. E. Pop, R. Dutton and K. Goodson, "Thermal Analysis of Ultra-Thin Body Device Scaling", Electron Devices Meeting, Technical Digest, IEEE International, pp. 36.6.1-36.6.4, Dec. 2003.
  4. S. Kumar et al., "Self-consistent and efficient electro-thermal analysis for poly/metal gate FinFETs", IEDM Tech. Dig, pp. 1-4, Dec. 2006.
  5. H. Gossner et al., "Unique ESD failure mechanism in a MuGFET technology", IEDM Tech. Dig, pp. 1-4, Dec. 2006.
  6. B. M. Tenbroek, M. S. L. Lee, W. Redman-White, J. T. Bunyan, and M. J. Uren, "Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques" IEEE Trans. Electron Devices, vol. 43, no. 12, pp. 2240-2248, Dec. 1996. https://doi.org/10.1109/16.544417
  7. J. H. Kim. S. Y Kim, "The Effect of Contact Boundary on Bulk Resistance in Hexagonal Shaped Source/Drain in FinFETs", International Technical Conference on Circuits Systems-Computers and Communications, pp. 366-369, June. 2015.
  8. J. C. Guo, "Halo and LDD Engineering for Multiple VTH High Performance Analog CMOS Devices", IEEE Trans on Semiconductor Manufacturing, vol. 20, no. 3, pp. 313-322, Aug. 2007. https://doi.org/10.1109/TSM.2007.901408
  9. M. M. Frank, "High-k/metal gate innovations enabling continued CMOS scaling", 2011 Proceedings of ESSDERC, pp. 25-33, Sept. 2011.
  10. S. Kolluri, K. Endo, E. Suzuki, K. Banerjee, "Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance", IEEE International Electron Devices Meeting, pp. 177-180, Dec. 2007.
  11. S. Makovejev, S Olsen, J. P. Raskin "RF Extraction of Self-Heating Effects in FinFETs", IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3335-3341, Oct. 2011. https://doi.org/10.1109/TED.2011.2162333
  12. U. S. Kumar, V. R. Rao, "A Thermal-Aware Device Design Considerations for Nanoscale SOI and Bulk FinFETs", Electron Devices, IEEE Transactions on, vol. 63, pp. 280-287, Dec. 2015.
  13. BSIM-CMG108.0.0 Technical Manual, Aug. 2014.
  14. TCAD Sentaurus User's Guide, Synopsys.
  15. P. M. Hall, "Resistance calculations for thin film patterns" Thin Solid Films, pp. 277-295, Sept. 1967.
  16. Ivanov, Valentin I., and M. K. Trubetskov. Handbook of conformal mapping with computer-aided visualization. CRC press, 1994.
  17. N Lu, S. J. Lee, R. A. Wachnik, "Symmetry Breaking in the Drain Current of Multi-Finger Transistors", Custom Integrated Circuits Conference IEEE, pp. 1-4, Sept. 2015.