전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제53권8호
  • /
  • Pages.49-58
  • /
  • 2016
  • /
  • 2287-5026(pISSN)
  • /
  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

링크 도선 길이를 고려한 고성능 비동기식 NoC 토폴로지 생성 기법

Link-wirelength-aware Topology Generation for High Performance Asynchronous NoC Design

  • 김상헌 (성균관대학교 정보통신대학) ;
  • 이재성 (성균관대학교 정보통신대학) ;
  • 이재훈 (성균관대학교 정보통신대학) ;
  • 한태희 (성균관대학교 정보통신대학)
  • Kim, Sang Heon (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Lee, Jae Sung (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Lee, Jae Hoon (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Han, Tae Hee (College of Information & Communication Engineering, Sungkyunkwan University)
  • 투고 : 2016.05.17
  • 심사 : 2016.07.29
  • 발행 : 2016.08.25
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

어플리케이션 특성에 따라 링크 대역폭 요구량이 다양하게 분포하는 이종 (heterogeneous) 아키텍처 기반 네트워크-온-칩 (Network-on-Chip, NoC) 설계에 있어 링크 지연 시간이 독립적으로 설정될 수 있는 비동기식 프로토콜을 적용할 경우 동기식 설계에 비해 성능 향상의 기회가 확대될 수 있다. 본 논문에서는 비동기식 NoC에서 각 링크의 대역폭 요구량과 도선 길이에 따른 지연 시간 모델을 제시하고 이를 최적화하는 simulated annealing (SA) 기법을 이용한 플로어플랜 기반 토폴로지 생성 알고리즘을 제안하였다. 생성된 토폴로지와 각 링크의 도선 길이를 기반으로 대응하는 도선 지연시간을 계산하고 로직 합성 단계를 거쳐 생성된 gate-level netlist와 표준지연시간 모델을 이용한 시뮬레이션을 통해 성능을 측정하였다. 링크 도선 길이를 고려하지 않은 일반적인 토폴로지 생성 알고리즘인 TopGen과 비교하여, 제안된 알고리즘이 다양한 어플리케이션 실험에서 평균 13.7% 지연 시간 단축 효과 및 처리량 측면 지표인 실행 시간에서 평균 11.8% 감소 효과가 있음을 확인할 수 있었다.

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.

키워드

참고문헌

  1. M. Krstic, E. Grass, F. K. Gurkaynak, and P. Vivet, "Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook," IEEE Design & Test of Computers, vol. 24, no. 5, pp. 430-441, Sept.-Oct. 2007. https://doi.org/10.1109/MDT.2007.164
  2. S. Hauck, "Asynchronous Design Methodologies : An Overview," Proceedings of the IEEE, vol. 83, no. 1, pp. 69-93, Jan. 1995. https://doi.org/10.1109/5.362752
  3. A. Lines, "Asynchronous interconnect for synchronous SoC design," IEEE Micro, vol. 24, no. 1, pp. 32-41, Jan.-Feb. 2004. https://doi.org/10.1109/MM.2004.1268991
  4. "International Technology Roadmap for Semiconductors," Semiconductor Industry Association, 2012.
  5. IBM Research, Introducing a Brain-Inspired Computer. (2014) [Online]. Available: http://www.research.ibm.com/articles/brain-chip.shtml.
  6. M. Imai and T. Yoneda, "Improving Dependability and Performance of Fully Asynchronous On-chip Networks," in Proceeding of IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 65-76, Apr. 2011.
  7. O. Naoya, A. Matsumoto, T. Funazaki and T.Hanyu, "High-Throughput Compact Delay-Insensitive Asynchronous NoC Router," IEEE Transactions on Computers, vol. 63, no. 3, pp. 637-649, Mar. 2014. https://doi.org/10.1109/TC.2013.81
  8. J. You, D. Gebhardt, and K. S. Stevens, "Bandwidth Optimization in Asynchronous NoCs by Customizing Link Wire Length," in Proceeding of IEEE International Conferfence on Computer Design (ICCD), pp. 455-461, Oct. 2010.
  9. Y. Bei, C. Song, S. Dong, S. Chen, and S. Goto, "Floorplanning and Topology Generation for Application-Specific Network-on-Chip," in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 535-540, Jan. 2010.
  10. D. Gebhardt, J. You, and K. S. Stevens, "Design of Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 9, pp. 1387-1399, Sept. 2011. https://doi.org/10.1109/TCAD.2011.2149870
  11. S. N. Adya and I. L. Markov, "Fixed-outline Floorplanning : Enabling Hierarchical Design," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6 pp. 1120-1135, Dec. 2003. https://doi.org/10.1109/TVLSI.2003.817546
  12. Z. Wang, J. Xu, X. Wu, Y. Ye, W. Zhang, M. Nikdast, X. Wang. and Z. Wang, "Floorplan Optimization of Fat-Tree-Based Networks-onChip for Chip Multiprocessors," IEEE Transactions on Computers, vol. 63, no. 6, pp. 1446-1459, Jun. 2014. https://doi.org/10.1109/TC.2012.295
  13. D. Rostislav, V. Vishnyakov, E. Friedman and R. Ginosar, "An Asynchronous Router for Multiple Service Levels Networks on Chip," in Proceedings of IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 44-53, Mar. 2005.
  14. J. J. H. Pontes, M. T. Moreira, F. G. Moraes, and N. L. V. Calazans, "Hermes-AA: A 65nm asynchronous NoC router with adaptive routing," in Proceedings of IEEE International SOC Conference (SOCC), pp. 493-498, Sept. 2010.
  15. D. Gebhardt, J. You, and K. S. Stevens, "Link pipelining strategies for an application-specific asynchronous NoC," in Proceedings of IEEE/ACM International Symposium on Networks on Chip (NoCS), pp. 185-192, May. 2011.
  16. M. E. Dean, T. E. Williams, and D. L. Dill, "Efficient Selftiming with Level Encoded 2-phase Dual-rail (LEDR)," in Proceedings of University of California/Santa Cruz Conference on Advanced research in VLSI, pp. 55-70, Apr. 1991.
  17. Y. Ar, S. Tosun, and H. Kaplan, "TopGen: A new algorithm for automatic topology generation for Network on Chip architectures to reduce power consumption," in Proceedings of International Conference on Application of Information and Communication Technologies (AICT), pp. 1-5, Oct. 2009.
  18. D. Bertsimas and J. Tsitsiklis, "Simulated annealing," Statistical Science, vol. 8, no. 1, pp. 10-15, Feb. 1993. https://doi.org/10.1214/ss/1177011077
  19. Silicon Integration Initiative. Nangate open cell library. (2008) [Online], Avaialable: http://www.si2. org/openeda.si2.org/projects/nangatelib, Accessed on: May 2016.
  20. R. P. Dick, D. L. Rhodes, and W. Wolf, "TGFF: Task Graphs for Free," in Proceedings of International Workshop on Hardware/Software Codesign (CODES/CASHE), pp. 97-101, Mar. 1998.