A Novel Compensator for Eliminating DC Magnetizing Current Bias in Hybrid Modulated Dual Active Bridge Converters

Abstract

This paper proposes a compensator to eliminate the DC bias of inductor current. This method utilizes an average-current sensing technique to detect the DC bias of inductor current. A small signal model of the DC bias compensation loop is derived. It is shown that the DC bias has a one-pole relationship with the duty cycle of the left side leading lag. By considering the pole produced by the dual active bridge (DAB) converter and the pole produced by the average-current sensing module, a one-pole-one-zero digital compensation method is given. By using this method, the DC bias is eliminated, and the stability of the compensation loop is ensured. The performance of the proposed compensator is verified with a 1.2-kW DAB converter prototype.

I. INTRODUCTION

Residential electricity consumption has been increasing all over the world for the past several years. This increasing electricity consumption trend is attributed to the increasing number of home appliances and consumer electronics. Thus, small power household PV generation systems (300W~2000W) have been widely encouraged for use in the residential sector to power these devices as an auxiliary power supply.

A fundamental type of household PV system [1] is shown in Fig. 1. This PV system uses a bidirectional converter to store solar energy in the battery when the output power of the PV panel is higher than the power absorbed by the load. In addition, the bidirectional converter transfers this stored energy to the load when the output power of the PV panel is lower than the power absorbed by the load. In high-voltage-ratio applications, the dual active bridge (DAB) converter, shown in Fig. 2, has attracted the attention of many researchers [2], [3]. In the early stages of development, the single phase shift modulation (SPSM) was generally used due to its simplicity in implementation and good dynamic response characteristic [4]. However, SPSM fails to provide a good efficiency characteristic when the voltage transfer ratio increases, especially at light loads [5]. When the performance of microcontrollers was improved and many of them were commercialized with moderate pricing, some complex control methods like triangular modulation (TRM), modified triangular modulation (MTRM) [6], and trapezoidal modulation (TZM) were proposed to improve the light load efficiency of DAB converters when the voltage transfer ratio increases [7]. Nowadays, in applications which require a large voltage transfer ratio, hybrid modulation which employs both SPSM and TRM is always used.

Fig. 1.Schematic of the household PV system.

Fig. 2.Schematic of the DAB converter’s power stage and its key waveforms.

However, the DC bias characteristics are seldom mentioned in these modulations. This is explained by the fact that the voltage-second products in these modulation methods are regarded as zero during a switching period [8]-[12]. Unfortunately, this assumption is not always satisfied in real applications because the voltage-second product is always unbalanced. Actually, this will happen in all of the power converters that employ high frequency transformers [13], [14]. At first, some DC bias compensation methods were proposed to suppress the DC bias in phase shift full bridge converters [15], [16]. The earliest control method to eliminate the DC bias of DAB converters was presented in [17]. However, only one operation condition is considered in this method, and a peak-current detector which is hard to realize in the DAB converters is needed. In [18], two different control loops (flux control and duty cycle based current mode control) were introduced, and a tertiary winding was added to inject a current equal to the DC bias. According to the description, if the output voltage needs to be controlled, there are three loops, which makes the stability of the DAB converter a serious problem. In the same year, a dual loop control method (including a loop to control the output voltage regulation) was introduced to suppress the DC bias [19]. The problem is that only the schematic of the dual loop control was given. A procedure for improving the stability of the introduced loop is not mentioned. In addition, these three methods can only be used in SPSM; they are are not the right choice for hybrid modulation schemes. The most recent article related to DC bias is [20]. However, this algorithm mainly focuses on the elimination of the transient DC bias to improve the transient response.

To overcome these problems, this paper proposes a novel DC bias compensation method to suppress the main DC bias in hybrid modulated DAB converters that employ TRM and SPSM. An average current sensing method is employed to detect the DC bias of the DAB converter. The procedure to achieve this average current sensing method is described in detail. Then a small signal model of the compensation loop is modeled. The design of the compensation loop is given. Finally, a prototype is built to demonstrate the validity of this method.

 

II. PROBLEMS CAUSED BY THE DC BIAS AND THE PROPOSED DC BIAS COMPENSATOR

A. Generation of the DC Bias

Fig. 2 shows a typical DAB converter without DC blocking capacitors. There are definitely two places that cause current DC bias; the primary side and the secondary side of the transformer. They are the power inductance L (including the leakage inductance of the transformer), and the secondary side magnetic inductance Lm2. Ideally, the primary side current has no DC bias, since the structure of the DAB converter is symmetrical. However, the DC bias of the magnetizing current appears in real applications. This is because that the voltage–second balances of the magnetic elements are not achieved. There are usually four reasons for these imbalances: 1) unbalanced pulse-width modulation (PWM) signals generated by the controller; 2) unbalanced parasitic parameters of the components, such as parasite resistance, parasite inductance and so on; 3) different switching ON/OFF characteristics; 4) nonlinearities of the magnetic cores.

Both L and Lm2 can produce DC biases if the voltage-seconds on them are unbalanced. The DC biases of L and Lm2 are affected by VAB(t) and VCD(t)/N. A problem is that if both of the primary side and the secondary side DC biases are compensated by control loops, there must be two loops to compensate the DC bias. This means that there is a very complex stability design problem. In fact, the secondary side DC bias can be suppressed very well without using a compensator. The DC bias on an inductor, caused by the parasite resistance imbalance of the full bridge, can be analyzed by the model shown in Fig. 3(a). When Q1 and Q4 are open, the resistance of the current path is R1. When Q2 and Q3 are open, the resistance of the current path is R2. A mismatch of R1 and R2 causes the DC bias of the inductor current. It is assumed that the current waveform is symmetrical. The DC bias caused by this mismatch can be expressed as:

Where:

Where Ts is the switching frequency. If R1 and R2 are not the same, x1 will not be the same as x2. Then there is a DC bias. Here R1 = 0.1, R2 = 0.2, Ts = 27µs, and V = 60V. The relationship between Ibias and L is illustrated in Fig. 3(b). It can be found that the DC bias of the inductor caused by a mismatch of the parasite resistances of the bridge legs is reversely proportional to the inductance.

Fig. 3.(a) Model of the parasite resistance mismatch. (b) Relationship between the DC bias and the inductance in this model. (c) Measured waveforms of the primary side current and the secondary side current.

This conclusion can be used in the DAB converter. The secondary side DC bias is caused by two factors. They are the inducted current of the primary side, and the DC bias of Lm2. However, the DC bias of Lm2 from the primary side gets through Lm2 at last. This is due to the fact that it causes a ripple on the battery side. This ripple increases the DC bias of Lm2 until the DC bias of Lm2 from the primary side is totally absorbed by Lm2. Therefore, the secondary side DC bias is entirely caused by the voltage-second imbalance of the secondary side bridge on Lm2. The model shown in Fig. 3 shows that the larger the inductance is, the smaller the parasite resistance imbalances’ effect becomes. The value of Lm2 in the prototype is 0.9 mH. It is big enough to suppress the DC bias caused by the mismatch of the parasite resistances. However, the primary side DC bias is affected by the parasite resistance mismatch largely because the value of L is about 14µH, and the voltage added to the power inductor is large during the operation of the DAB converter. One of the test results of the DC biases on the primary side and the secondary side is shown in Fig. 3 (c). In this figure, the DC bias on the primary side is much larger when both of them are not compensated.

B. Problem Caused by the DC Bias

A conventional controller stabilizes the output voltage Vo of the DAB converter by controlling the phase shift between VAB and VCD, the inner duty cycle D1 of VAB, and the inner duty cycle D2 of VCD [6]. Since the controller has no information on the DC bias, it cannot rebalance the voltage–second product of the magnetic elements. Therefore, the conventional controller cannot remove the DC bias of the primary side current.

When DC bias is generated, the primary current increases in either the positive direction or the negative direction. The first problem is that it increases both the conduction loss and the current stress. Another problem is the saturation of the magnetic core. The third problem is its effect on the ZVS characteristics of the MOSFETs. Finally, it also causes audio-frequency noise. In the design of the DAB converter, the ZVS is an important problem that needs to be considered. If DC bias exists, the current in one of the upper-left-side MOSFETs increases at the switching-on transient. This phenomenon increases the switching loss. To verify the bad effect of the DC bias, an experiment is conducted on a 1.2kW (the maximum power when the input voltage and the output voltage are 106V and 60V) prototype. The input voltage is 40V and the output voltage is 60V (under this condition, the maximum power is about 450W). The output voltage is controlled by a voltage-mode controller, which is achieved in a TMS320f28335 digital signal processor. Fig. 4 shows the efficiencies of the converter both with and without the DC bias. It can be seen that the DC bias decreases the overall efficiency of the DAB converter. For the aforementioned reasons, there is no doubt that the DC bias must be eliminated to keep the reliability and efficiency of DAB converters.

Fig. 4.Comparison between the measured efficiencies of the compensated and the uncompensated DAB converter.

C. Proposed Compensator

The DAB converter with the proposed compensator is shown in Fig. 5. The current sensing module detects the current of I1. Then the detected current is chopped into two parts. The first part is defined as I1-Q4, and the second part is defined as I1-Q2 (these two parts are synchronous with the driver signals of Q4 and Q2). The difference between I1-Q4 and I1-Q2 is averaged by a low pass filter which consists of Rf1, Rf2 and Cf1. The averaged values of I1-Q4 and I1-Q2 are set as I1-Q4,av and I1-Q2,av. The basic control logic is that if I1-Q4,av > I1-Q2,av, which means that the DC bias is positive, the duty cycle of Q1 is decreased with to suppress this DC bias. The magnitude of the primary current is balanced after several switching periods. There are two control loops which eliminate the DC bias and stabilize the output voltage. The loop of the compensator consists of two parts. They are a average current sensing module and a PI module (achieved in a TMS320f28335). The average current sensing module consists of a current sensing module, two MOSFETs, and a low pass subtracter. The two MOSFETs are driven by the gate drive signals of Q4 and Q2. The main loop of the DAB converter consists of 5 modules to achieve a hybrid modulation which employs TRM and SPSM. The specifications of this loop are not discussed here.

Fig. 5.(a) Schematic of the DAB converter with the proposed DC bias compensation. (b) Schematic of the proposed average current sensing module.

The average current method detects the average value of I1-Q4,av(t) - I1-Q2,av(t) . This average value has a relationship with the DC bias, and is expressed as:

Where k is a constant corresponding to the modulation method. In this paper, SPSM and TRM are used, and the calculation of k is dependent on the modulations. The parameter k is the small signal gain from the average currents’ difference to the real average current value. In SPSM, the behavior of the small signal gain can be modeled as shown in Fig. 6(a). This behavior is based on the assumption that the inductor current is symmetrical. If there is a small signal perturbation ÎL,av on IL,av there will be an increment of ÎL,av on I1-Q4. Because the duty cycle of the drive signal on Q4 is 50%, it can be seen that the gain from ÎL,av to Î1-Q4,av is 0.5. It can also be seen that the gain from ÎL,av to Î1-Q2,av is -0.5 . That is to say k = 1. In TRM, when M < 1 (M = VCD/VAB = NV2 /V1), the behavior of the small signal gain can be modeled in Fig. 6(b). In the stage when VAB(t) is zero, the inductor current does not flow out of the left-side bridge. It flows around Q2 and Q4. Therefore, it can be seen that the gain from ÎL,av to Î1-Q4,av is 0.5D1, and the gain from ÎL,av to Î1-Q2,av is -0.5D1. That is to say k = D1. As shown in Fig. 6(c), it can be derived that k = D1 when M > 1. In fact, SPSM can be regarded as a case of D1 = D2=1. Therefore, it can be seen that:

Fig. 6.Small signal relationships between IL,av(t) and I1-Q4,av(t) in (a) SPSM (b) TRM, when M < 1 (c) TRM, when M > 1.

 

III. MODELS OF THE DC BIAS IN THE DAB CONVERTER

A. Small Signal Behaviors of the DC Bias with Respect to the Duty Cycles

In the primary side bridge, the small signal behaviors of the DC bias with respect to the duty cycles can be seen in Fig. 7. In SPSM, if there is a duty cycle increment on Q1, the DC bias increases. Then, the average currents of I1-Q1,av and I1-Q4,av increase accordingly. On the contrary, the average currents of I1-Q2,av and I1-Q3,av decrease. Therefore, if the processor detects that the DC bias is negative, it should increase the duty cycle of Q1 to compensate the DC bias, and vice versa. The same logic can also be used in the control of TRM to eliminate the DC bias. However, the control loop has a possibility of oscillating. Therefore, the small signal model in the frequency domain must be observed.

Fig. 7.Small signal relationships between d1(t), IL,av(t), I1-Q4,av(t), and I1-Q2,av(t) in (a) SPSM (b) TRM, when M < 1 (c) TRM, when M > 1.

B. Relationships between the DC Bias and the Duty Cycles in the Frequency Domain

The hybrid modulation scheme used in PV systems employs TRM and SPSM. These two modulations produce different inductor current shapes. Therefore, the traditional geometry method used in [15] is not good for obtaining the transfer function from the duty cycle of d1 to the bias current. In SPSM, the state space averaging method is used in a switching period as:

Where IL(t) is the current in the primary side inductor, A is the amplitude of VAB(t), B is the amplitude of VCD(t), and Rpara is the total parasite resistance of the DAB converter (the calculation of Rpara can found in [22]). It is defined as:

Where:

Where Rswitch is the on-resistance of the power switch, RL is the parasite resistance of the power inductor, Rtr1 is the parasite AC resistance of the transformer on the primary side, Rtr2 is the parasite AC resistance of the transformer on the secondary side, RPCB,primary is the AC resistance of the PCB wire on the primary side, and RPCB,secondary is the AC resistance of the PCB wire on the secondary side. Then, the averaged equation can be derived from (6) as:

In (10), IL,av(t) and d1(t) can be substituted by IL,av + ÎL,av and d1 + . Where IL,av is the steady state part of IL,av(t), ÎL,av is the small signal perturbation on IL,av, d1 is the steady state part of d1(t), and is the small signal perturbation on d1. Therefore:

Then, the small signal transfer function from to ÎL,av in the Laplace domain is:

When in TRM and M < 1, the state equations can be expressed as:

Then the averaged equation can be derived as:

In (14), IL,av(t) and d1(t) can be substituted with IL,av + ÎL,av and d1 + . Where IL,av is the steady state part of IL,av(t), ÎL,av is the small signal perturbation on IL,av, d1 is the steady state part of d1(t), and is the small signal perturbation on d1. Therefore:

Then the small signal transfer function from to ÎL,av in the Laplace domain is:

When in TRM and M > 1, the state equations can be expressed like those in SPSM. By using the same process, it can be obtained that:

Then the averaged equation can be derived as:

In (18), IL,av(t) and d1(t) can be substituted with IL,av + ÎL,av and d1 + . Where IL,av is the steady state part of IL,av(t), ÎL,av is the small signal perturbation on IL,av, d1 is the steady state part of d1(t), and is the small signal perturbation on d1. Therefore:

Then the small signal transfer function from to ÎL,av in the Laplace domain is:

It can be found that all of the transfer functions from the duty cycles to the DC bias are one-pole functions. The positions of both poles are Rpara/(2πL). Therefore, in the design of the compensator, the position of the pole caused by the average current sensing module should be made to move away from Rpara/(2πL) to avoid oscillation.

The DC gains of (12), (16), and (20) are found to be 2A/Rpara, A/Rpara, and A/Rpara, respectively. They are finite, which means that the DC bias cannot be eliminated very well. Therefore, the integration must be done in the TMS32f28335.

 

IV. DESIGN OF THE DC BIAS COMPENSATOR

A. Model of the Compensator

The DC bias compensator is designed based on the proposed small signal model. The bias compensator is designed as follows:

Where kcomp/a is the high-frequency gain of the compensator, and a is the position of the zero. The compensator is a PI controller. The integration can be expressed as:

Where e(τ) is the error signal between IQ1, and IQ3. This equation means that the integration can be achieved in the DSP. Then the PI can be expressed in the DSP as:

The compensation is designed according to the positions of the poles produced by the average current sensing module and . The transfer function of the average current sensing module is expressed as:

Where Gm is the gain of the mutual inductor. Then, the loop gain of the compensator is expressed as:

The main specifications and parameters of the prototype’s power stage are summarized in Table I. The total parasite resistance is about 0.16 Ω . By inserting Rpara = 0.16Ω , L = 14μH into (26), the position of the first pole is obtained at 1.137kHz. To get the average values of IQ2 and IQ4, Rf2 = 1kΩ and Cf = 0.2uF are used. They produce a pole at a frequency of 796Hz. The positions of the two poles are very close. The stability is not good because the phase-frequency characteristic decreases too fast to a value of 180°. Therefore, the zero of the PI is set at 796Hz to offset the pole of the average current sensing module. That is to say a = 2 × 10-4. After the determination of the poles’ positions, the gain at a frequency of 6.28Hz must be determined to ensure the phase margin of the control loop. The gain at a frequency of 6.28Hz is expressed as:

The gain at a frequency of 6.28Hz depends on the modulation methods of the DAB converter. Therefore, the DSP should give different values to kcomp depending on the modulation methods. Finally, Gloop(6.28Hz) is set at 45dB to ensure a phase margin of 53 degrees. A bode plot of the designed compensator is shown in Fig. 8.

TABLE IMAIN SPECIfiCATIONS AND PARAMETERS OF THE PROTOTYPE CONVERTER’S POWER STAGE

TABLE IICOMPONENTS OF THE PROTOTYPE

Fig. 8.Target Bode plot of the compensation loop.

B. Interaction between the Compensator and the DAB Converter

When IL,av varies, IQ1,av and IQ2,av vary. The variations of IQ1,av and IQ2,av affect the input power accordingly. If the input power varies, the output power is affected. Then the variation of the output power leads to a variation of the output voltage. On the other hand, the output voltage affects IL,av in turn. If there is a small signal increment on VCD, there is a small signal increment on the slope of IL. Then, IL,av varies. That is to say, if the duty cycle varies, the loop of IL,av → Vo → VCD → IL,av is affected. If IL,av is affected, the loop of the compensator is affected. The phenomenon derived by this logic reasoning is called interaction between the loops (IBL). By this logic reasoning, it can be found that there is possibility to make the DAB converter unstable. However, the IBL does not happen in real applications because the small signal gain from Vo to IL,av exists only in the condition where there is a step change in Vo. Two simulations in Saber software are made. The first simulation, which is under the condition of a step change, is shown in Fig. 9(a). The second simulation, which is under the condition of a continuous change is shown in Fig. 9(b). It can be seen that IL,av varies instantaneously when VCD has a step change. The simulation of the step change is coincident with the analysis. However, if there is a continuous change, IL,av does not vary any more. If a small signal perturbation is added to Vo (exaggerated perturbation), the variation of Vo which is shown in Fig. 9(c) is continuous. Then, the small signal gain from Vo to IL,av is zero. Therefore, there is no need to consider the effect from Vo to IL,av. That is to say, the loop of IL,av → Vo → VCD → IL,av does not exist in the small signal model. In other words, the IBL does not exist in the DAB converter which uses the DC bias compensator. In the design of the DAB converter with the proposed compensator, it is only necessary to ensure the stabilities of the compensator loop and the loop which stabilizes the output voltage.

Fig. 9.Simulated results from saber. (a) Relationship between the DC bias and VCD when Vo has a step change. (b) Relationship between the DC bias and VCD when Vo has a continuous change. (c) Relationship between the DC bias and VCD when Vo has a small signal perturbation (the amplitude of the small signal perturbation is exaggerated).

 

V. EXPERIMENTAL RESULTS

The hybrid modulation scheme and the proposed DC bias compensation method in TRM and DPSM are implemented in a TMS320f28335 digital signal processor (DSP). This is a 32 bits processor with a Single-Precision Floating-Point unit. It also has a 12 bits ADC which can acquire at least 0.8mV of voltage. Therefore, the proposed modulation scheme and the compensation methods can be achieved by this DSP. In the power stage, IRFB4321 MOSFETs are used as power switches due to their low on-resistance. All of the power switches consist of two MOSFETs. In the transformer, Litz wires are used to reduce the copper loss. The mutual inductor’s turn ratio is selected as 1:2000, the gain of AD620 is 2V/V, and Rsense = 20Ω. Qs1 and Qs1 are 0803GMT MOSFETs. Fig. 10 (a) and (c) show the inductor current and I1 of the uncompensated DAB converter during SPSM. It can be seen that the upper-peak current value is 12A, while the lower-peak current is 16A, and that I1 has a two-period oscillation, which means that DC bias exists in the inductor current. Fig. 10 (b) and (d) show the inductor current and I1 of the compensated DAB converter during SPSM. Although it can be seen that the upper-peak current value is 13.5A, while the lower-peak current is 14.8A, and that I1 has a very small two-period oscillation, the DC bias is definitely suppressed because the inductor current is a little asymmetrical. Therefore, the upper and lower peak current values are not exactly equal to each other. Fig. 11 (a) and (c) show the inductor current and I1 of the uncompensated DAB converter during TRM. In TRM, the DC bias is slightly bigger than that in SPSM. The upper-peak current value is 5.4A, while the lower-peak current is 13A. It can be seen that there is a very big two-period oscillation in I1. After compensation, the upper peak current and the lower peak current are both 9.7A, and the two-period oscillation is eliminated as shown in Fig. 11 (b) and (d). To further demonstrate the improvements of this compensation, the transitions from the uncompensated conditions to the compensated conditions in both the SPSM and the TRM are shown in Fig. 12 (a) and (b). During the transitions, a digital filter is used. The logic is that, in TRM, if the sensed current value gets into the preset region of SPSM, and the variable i increases by 1. If the sensed current value gets out of this preset region of SPSM, the variable i decreases by 1. When i increases to 5, the filter allows the transition from SPSM to TRM, and vice versa. Finally, the efficiencies of the compensated and uncompensated DAB converters are compared in Fig. 13. This comparison shows that the improvements exist in all of the conditions. When M = 2, the improvement is relatively small because the DC bias is small. However, when M = 1 and M = 0.6 , the improvements increase to an average value of 2%.

Fig. 10.Key waveforms for DAB during SPSM, M = 1.3 Po = 227W, Vin = 43V , Vo = 58V . (a) IL without compensation. (b) IL with compensation. (c) I1 without compensation (d) I1 with compensation.

Fig. 11.Key waveforms for DAB during TRM, M = 1.3 Po = 205W, Vin = 43V , Vo = 58V . (a) IL without compensation (b) IL with compensation. (c) I1 without compensation. (d) I1 with compensation.

Fig. 12.Key waveforms of the transitions from the uncompensated condition to the compensated condition in (a) SPSM. (b) TRM.

Fig. 13.Efficiency comparisons between the compensated converter and uncompensated converter when Vo = 58V. (a) M = 2. (b) M = 1. (c) M = 0.6.

 

VI. CONCLUSION

It is found that the efficiency of a DAB converter decreases when DC bias exists. To overcome this problem, this paper proposes a DC bias compensation method to suppress the DC bias of hybrid modulated DAB converters that employ TRM and SPSM. Small signal models of the compensation loops in both the SPSM and the TRM are made to ensure the stability of the proposed method. The design of this compensation is given. Experimental results are given to show that the compensation method can work properly and that the overall efficiency of the DAB converter is improved by about 2% when the proposed method is used.