I. INTRODUCTION
Recently, light-emitting diodes (LEDs) have become popular solid-state lighting sources [1]-[3], as have AC/DC LED drivers. However, distortion of the input current resulting from nonlinear components in the AC power supply equipment, results in a lower power factor (PF). In addition, there is still some input current distortion due to the system’s parasitic parameters and non-ideal characteristics, especially in the zero-crossing zone of the input voltage [4], [5]. The increasing demands on the conversion efficiency and power factor of power electronic equipment have resulted in the birth of harmonic standards such as Energy Star 2.0 [6], IEC 1000-3-2 and IEEE/ANSI 519.
Many academic studies have been conducted to reduce input current distortion to obtain much lower THD and a higher power factor. In [5], the phase delay technique is adopted to compensate for the phase lead, which reduces both the zero-crossing distortion and the THD. However, the dead angle of the input current, which results in higher THD, has not been completely eliminated. The input current zero-crossing distortion is reduced by detecting the dead zone boundary, and the system switched the topological structure due to the auxiliary switch in [7]. However, there is a lot of input current distortion during the auxiliary switch point. Moreover, the additional control circuit and discrete devices increase the power consumption and cost. The study in [8] adds a periodic self-starting timer block to force the power switch “ON”, solving the dead angle problem of the input current and significantly reducing the distortion near the input voltage zero-crossing points. However, this additional compensation module cannot control the turn-on time of the power switch according to the input voltage in the dead region. As a result, it is limited in terms of obtaining much lower THD.
This paper proposes a novel zero-crossing compensation scheme applied to fixed off-time controlled high power factor AC-DC LED drivers. By detecting the zero-crossing boundary, the proposed ZCC circuit compensates the control signal, which modulates the power switch in the dead region. With further optimization of the parameters of the ZCC circuit, the dead zone is eliminated and lower THD is achieved.
In Section II, the fixed off-time controlled high PF AC-DC LED driver is described. The ZCC principle and the detailed parameter optimization procedure are described in Section III. Section IV demonstrates the effectiveness of the proposed method with the proposed zero-crossing compensation for improving the input current distortion through tests of the real circuit. Finally, section V presents some conclusions.
II. FIXED OFF-TIME CONTROLLED SYSTEM
A. System Construction
The fixed off-time controlled system is based on the Flyback topology, which consists of a rectifier bridge, RCD circuit, transformer, NMOS power switch, and a series of diodes, resistors and capacitances, as is shown in Fig. 1. The resister RS detects the primary-side current and achieves VCS. The S/H (sample and hold) module samples VCS and outputs the signal VH. The feedback detection module processes the signal DSEN from the auxiliary winding and obtains the demagnetization time TDemag, over voltage protection (OVP) and short circuit protection (SCP) signal. The module Gm amplifies the difference between Vref and VFB, which is equal to VH multiplied by TDemag. The zero-crossing compensation (ZCC) module is attached to the output of the OTA. The PFC COMP module compares the signals VCOMP and VRAMP from the PFC ramp module, and exports the comparison result Vint to control the module TOFF. TOFF is a multi-vibrator which outputs VTOFF. VTOFF has a low level and maintains this state for a fixed period of time when Vint changes to a high level. Then it turns to a high level and waits for the next high level of Vint. The logical control module determines whether DRV follows VTOFF. DRV is always kept low when the enable signal EN is at a high level, or it follows VTOFF when EN is invalid at a low level. The PFC Ramp module generates a fixed slope ramp signal when DRV is high and keeps a low voltage when DRV is low. The driver module is a driving circuit, which aims at enhancing the driving capability of DRV to drive the power MOSFET. When DRV is high, VH samples VCS timely and holds the last sample value when DRV is at a low level.
Fig. 1.Fixed off-time system structure.
B. Ideal Operation Principle
Ideally, the fixed off-time controlled system is operated as the work waveform shown in Fig. 2. VH samples VCS when DRV is high and holds the last sampling value when DRV is low. Then it is multiplied by TDemag from the Feedback Detection module and obtains the signal VFB. Therefore, VFB can be expressed as:
where, Ippk is the peak current of the primary-side. RS is the primary side sampling resistor. n is the turns ratio between the primary and secondary coil. TDemag is the demagnetization time of the auxiliary winding, and TS is the switch period.
Fig. 2.The ideal work waveform.
Since there is a large capacitance attached to the port VCOMP, VCOMP is relatively constant. During the long period from t to t+Δt, equation (2) can be easily achieved.
where, Vref is the reference voltage contacted to the positive input of OTA.
When DRV is high, the PFC Ramp produces a fixed slope ramp signal compared with VCOMP. When VRAMP reaches VCOMP, Vint becomes high level and triggers the TOFF module. Meanwhile, the TOFF outputs a fixed time low voltage and then returns a high voltage while waiting for the next high level of the trigger signal Vint. Therefore, the modulation signal VTOFF is achieved. Under normal working conditions, there is no OVP or SCP signal. Therefore, EN is always invalided and the DRV signal follows the signal VTOFF.
The average output current can be described as:
where, Iout is the average output current. Ispk is the peak current of the second-side. RS is the sampling resistor contacted to the power switch. Therefore, the average output current can be kept constant.
According to the above analysis, since VRAMP increases at a fixed slope when DRV is high, the power switch conduction time can be expressed as:
where, Ton is the conduction time of the power switch. k is the constant coefficient related to the fixed slope of VRAMP. Thus, the primary current can be shown as:
where, Vin is the amplitude of the input line voltage. ω is angular frequency of the input voltage. Lp is the value of the primary inductance.
Therefore, the average input current meets the following condition:
where, Toff is the switch off period, and Iin is the average input current.
Ideal work waveforms within one period are shown in Fig. 3. VCOMP is kept constant and the average input current Iin follows the sinusoidal input voltage.
Fig. 3.Ideally work waveforms within one period.
In this cycle, the normal power switch modulation signal is achieved, as well as a high power factor and a constant output current.
C. Practical Operation Phenomenon without the Proposed Zero-Crossing Compensation
However, due to the parasitic parameter and nonlinear characteristics of the system, there is a dead zone when the input voltage approaches the zero-crossing region [5], [9]-[10], and VCOMP is not constant during the entire input voltage range. Due to the variable of VCOMP, in the dead zone, the power switch is kept ‘OFF’ and the primary current is always zero. The IC driver cannot generate the normal modulation signal to drive the switch ‘ON’ or ‘OFF’.
A practical waveform without the proposed zero-crossing compensation is presented in Fig. 4. DRV is the modulation signal of the power switch. TOFFR_AMP is the signal to generate the fixed off-time signal, and ip is value of the primary current. Undoubtedly, there is a dead zone where the input current cannot follow the sinusoidal input voltage in the entire range, which results in a heavy current distortion and decreases the power factor.
Fig. 4.The simulation results.
In order to decrease the input current distortion and to increase the power factor, this paper proposes a novel compensation circuit to remove this dead region.
III. ZERO-CROSSING COMPENSATION ANALYSIS
A. Zero-Crossing Compensation Principle
To solve the dead zone problem, a novel zero-crossing compensation module is introduced. As shown in Fig. 1, the proposed zero-crossing compensation is connected to the output of the OTA. The proposed ZCC circuit is shown in Fig. 5. By detecting VCOMP and comparing it with the preset voltage, the ZCC circuit recognizes the boundary of the dead zone and compensates the value of VCOMP. Consequently, VCOMP can be kept relatively constant and the system can output a normal modulation signal to drive the power switch in the entire input voltage range.
Fig. 5.The proposed zero-crossing compensation circuit.
According to Fig. 5, MP1 and MP2 make up a current mirror. MN5 is biased by a signal Bias. MN6 and MN8 are controlled by enabling signal EN1, which is invalid and maintains a low voltage under normal operation conditions. COMP is a comparator. The resistor R3 and the PNP transistor Q2 compose a voltage reference. The voltage reference V+ is connected to the positive input of the comparator COMP. Thus, V+ meets:
where, VEB is the voltage drop between the emitter and the base of the transistor Q2. I1 is the current through R3 and Q2.
The output voltage VCOMP is a feedback signal which connects to the negative input of COMP. When VCOMP is lower than V+, VCOMP can be expressed as:
where, KR = R2/(R1+R2), and VDD is the supply voltage of the ZCC circuit. Therefrore, the compensation module is affected by V+ and KR.
In the real circuit, the external compensation capacitor CP should to be taken into account as shown in Fig. 5. Therefore, the output voltage of the compensation module can be rewritten as:
Then, the time domain expression of the right branch circuit in Fig. 5 can be expressed as:
where, vC(t) is the instantaneous value of VCOMP. The ZCC circuit can only work when VCOMP is lower than V+. Therefore, the output voltage vC(t) of the ZCC circuit can be expressed as:
where, Kτ=(R1×R2)/(R1+R2), KR=R2/(R1+R2) and V+=I1×R3+VEB. VCOMP keeps jumping between vC(t) and VCOMP_0 (VCOMP_0 is the output voltage of the OTA module in Fig.1, when the ZCC circuit is not taken into account.). Finally, the complete expression of VCOMP can be described as:
As a result, VCOMP can be kept relatively constant during the entire input voltage range. In addition, the dead zone can be eliminated by optimizing VCOMP.
B. Zero-Crossing Compensation Circuit Optimization
From equation (12), VCOMP is related to the coefficients KR and Kτ. From equation (6), VCOMP influences the average input current. With different values of KR and Kτ, VCOMP can be variable after compensation, as well as the average input current iin within the zero-crossing zone. Fig. 6 shows different average input current waves with various values of KR and Kτ .
Fig. 6.Different input current waveforms with variable KR and Kτ.
In order to simplify the coefficients KR and Kτ, the value of R2 was set as 1. As shown in Fig. 6, when KR=1/6 and Kτ=5/6, in every half cycle, the input current can generally follow the input voltage’s change. However, the input current wave has a distortion about half the time. Therefore, this set of data cannot solve the input current distortion problem near the zero-crossing zone. When KR=2/11 and Kτ=9/11, in every half cycle, the input current is similar to a sinusoid wave. However, there is still distortion about two fifths of the time. When KR=1/5 and Kτ=4/5, in every half cycle, the input current is more similar to a sinusoid wave and the distortion zone is decreased to about one tenth of the time. Therefore, in this set of data, the distortion can almost be ignored. With further increasing of KR and decreasing of Kτ, when KR=2/9 and Kτ=7/9, the input current wave is in accordance with a sinusoid wave and has almost no distortion. When KR=1/4 and Kτ=3/4, the input current wave is also sinusoid and has almost no distortion. However, the average input current is much higher when compared with the last set of data.
According to the above discussion, with the proposed ZCC module, the input current distortion during the dead zone can be effectively solved. By optimizing the two coefficients, the simulation results are presented as Fig. 7. With the proposed ZCC module, the input current is no longer zero in the dead zone and the average input current can follow variations of Vin.
Fig. 7.Transient simulation results of primary current iP and DRV with proposed zero-crossing scheme.
IV. EXPERIMENT RESULTS
The IC is implemented in HHNEC 0.5μm 5V/40V HVCMOS process. A micro-graph of the fabricated chip is shown in Fig. 8, and the die size with PADs is 1950μm×2730μm.
Fig. 8.Micrograph of the fabricated chip.
A test circuit prototype of the designed chip is shown in Fig. 9. The AC operating voltage of the PCB is 85V~265V and the output power is 7~12W.
Fig. 9.Photograph of the test circuit prototype.
A. Test waveforms
Fig. 10 shows the gate voltage VGATE of the power switch MOSFET, and VCS is the multiplication of ip and RS, in which iP is the current flowing through the primary-side inductance, and RS is the primary-side current sensing resistor. Obviously, the envelope of the primary peak current presents a sinusoidal waveform and there is no dead zone around the zero-crossing point. The IC driver can output a normal modulation signal in the entire input range and fix the off-time in 10.7μs, even in the zero-crossing region. As a result, high power factor and lower THD are achieved in the fixed off-time controlled high power factor LED driver with the proposed zero-crossing compensation scheme.
Fig. 10.The test waveform of the driving signal VGATE and the voltage drop VCS of primary sampling resistor RS.
Fig. 11(a) shows test waveforms of the input AC voltage Vin and current Iin under AC sources of 110V/60Hz, while Fig. 11(b) shows test waveforms of the input AC voltage Vin and current Iin under AC sources of 220V/50Hz. Clearly, the test waveforms of the input AC current Iin present sinusoidal waveforms and there is no obvious dead zone around the zero-crossing point under both 110V/60Hz and 220V/50Hz in Fig. 11.
Fig. 11.The test waveforms of input AC voltage Vin and current Iin.
B. The System Performance with Different Inputs
The load is composed of 5~10 cascaded 3W LEDs. Fig. 12 shows the output current, PF, THD and conversion efficiency under four different inputs and different numbers of LED loads. As shown in Fig. 12(a), the output current is slightly affected by different output powers. In Fig. 12(b), the average PF under 85V/60Hz AC and 110V/60Hz AC inputs are 2~3% larger than that under 220V/50Hz AC, and 3~4% larger when compare to the 265V/50Hz AC input condition. As shown in Fig. 12(c), fluctuations in the THD are relatively mild under 220V/50Hz AC and 265V/50Hz AC with load changes, around the center value 10%. However, they are fairly obvious under 85V/60Hz and 110V/60Hz, from 5.5% to 15.1%. Finally, the conversion efficiency is above 82.5% under different input voltages and loads, as shown in Fig. 12(d).
Fig. 12.The system performance with 85V/60Hz, 110V/60Hz, 220V/50Hz and 265V/50Hz inputs voltage.
Finally, Table I summarizes a comparison of the signal stage AC/DC converters presented in [11], [12] and [13] with the proposed converter in terms of circuit implementation and performance. The proposed converter achieves a relatively constant output current (=420mA) and a high efficiency (>82%). The efficiency obtained in this paper is equivalent to the typical efficiencies obtained in [11] and [12]. However, it is slightly lower than the LED Driver presented in [13]. Nevertheless, the key point of the proposed ZCC scheme in this paper is to improve the power factor (PF) and to decrease the THD rather than increase the efficiency. From Table I, it can be seen that the LED Driver with zero-crossing compensation can obtain a high PF above 0.95 and a maximum of 0.999 which is larger than the LED Drivers presented in [11], [12] and [13]. Meanwhile, the average THD is decreased to approximately 10% which is obviously lower than that in [12] and [13]. With the proposed ZCC scheme in a fixed off-time controlled high power factor AC/DC LED driver, the dead zone can be completely eliminated by further optimization of KR and Kτ. Thus, the average input current can always follows the input voltage even in the zero-crossing zone.
TABLE IPROPOSED CONVERTER COMPARED WITH SOME PUBLISHED APPROACHES
V. CONCLUSION
This paper proposes a fixed off-time controlled high power LED driver with the proposed zero-crossing compensation. Based on the designed circuit, this paper verifies the feasibility of this compensation strategy, discusses the main parameters of the dead region, and optimizes the average input current waveform. The ZCC principle and the detail parameter optimization process are described. Finally, the chip is implemented using HHNEC 0.5μm 5V/40V HVCMOS, and the chip layout area is 1950μm×2730μm. Experimental results show that at 85-265V/AC input voltage and 7-12W output power, the system with the proposed zero-crossing compensation can obtain a high PF above 0.955, with a maximum of 0.999, and an average THD of 10%, with a minimum of 5.5%.
참고문헌
- M. S. Shur, and R. Zukauskas, "Solid-state lighting: Toward superior illumination," Proceedings of the IEEE, Vol. 93, No. 10, pp. 1691-1703, Oct. 2005. https://doi.org/10.1109/JPROC.2005.853537
- M. Wendt and J. -W. Andriesse, "LEDs in real lighting applications: From niche markets to general lighting," in Conference Record of the 2006 IEEE Industry Applications Conference Forty-First IAS Annual Meeting, pp. 2601-2603, 2006.
- S. Muthu, F. J. P. Schuurmans, and M. D. Pashley, "Red, green, and blue LEDs for white light illumination," IEEE J. Sel. Topics Quantum Electron., Vol. 8, No. 2, pp. 333-338, Mar./Apr. 2002. https://doi.org/10.1109/2944.999188
- X. Wu, J. Yang, J. Zhang, and Z. M. Qian, "Variable on-time (VOT)-controlled critical conduction mode buck pfc converter for high-input AC/DC HB-LED lighting applications," IEEE Trans. Power Electron., Vol. 27, No. 11, pp. 4530-4539, Sep. 2012. https://doi.org/10.1109/TPEL.2011.2169812
- J. Sun, "On the zero-crossing distortion in single-phase PFC converters," IEEE Trans. Power Electron., Vol. 19, No. 3, pp. 685-692, May 2004. https://doi.org/10.1109/TPEL.2004.826491
- ENERGY STAR® Program Requirements for Single Voltage External AC-DC and AC-AC Power Supplie: Eligibility Criteria Version 2.0. http://www.energystar.gov/ia/partners/prod_development/revisions/downloads/eps_spec_v2.pdf, Jul. 23, 2008.
- X. Xie, C. Zhao and L. Zheng, and & S. Liu, "An improved buck PFC converter with high power factor," IEEE Trans. Power Electron., Vol. 28, No. 5, pp. 2277-2284, May 2013. https://doi.org/10.1109/TPEL.2012.2214060
- Y. Li, Y. Yang, Z. Zhu, and W. Qiang, "Zero-crossing distortion analysis in one cycle controlled boost PFC for low THD," in Proc. ASICON, pp. 661-664. 2011.
- K. D. Gussemé, D. M. Van de Sype, A. P. Van den Bossche, and J. A. Melkebeek, "Input-current distortion of CCM boost PFC converters operated in DCM," IEEE Trans. Ind. Electron., Vol. 54, No. 2, pp.858-865, Apr. 2007. https://doi.org/10.1109/TIE.2007.892252
- L. Huber, L. Gang, and M. Jovanovic, "Design-oriented analysis and performance evaluation of buck pfc front-end," IEEE Trans. power Electron., Vol. 25, No. 1, pp. 85-94, Jan. 2010. https://doi.org/10.1109/TPEL.2009.2024667
- J. T. Hwang, M. S. Jung, D. H. Kim, J. H. Lee, M. H. Jung, and J. H. Shin, "Off-the-line primary side regulation LED lamp driver with single-stage PFC and TRIAC dimming using LED forward voltage and duty variation tracking control," IEEE J. Solid-State Circuits, Vol. 47, No.12, pp. 278-280, Dec. 2013.
- S. Jung and G. Cho, "Transformer coupled recycle snubber for high-efficiency offline isolated LED driver with on-chip primary-side power regulation," IEEE Trans. Ind. Electron., Vol. 61, No. 12, pp. 6710-6719, Dec. 2014. https://doi.org/10.1109/TIE.2014.2316221
- H. H. Chou, Y. S. Hwang, and J. J. Chen, "An adaptive output current estimation circuit for a primary-side controlled LED driver," IEEE Trans. Power Electron., Vol. 28, No. 10, pp. 4811-4819, Oct. 2013. https://doi.org/10.1109/TPEL.2012.2236581