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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Physical-Aware Approaches for Speeding Up Scan Shift Operations in SoCs

  • Lee, Taehee (Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, Rep. of Korea, the SOC design team in system LSI, Samsung Electronics) ;
  • Chang, Ik Joon (Department of Electronics and Radio Engineering, Kyunghee University) ;
  • Lee, Chilgee (Department of Semiconductor Systems Engineering, Sungkyunkwan University) ;
  • Yang, Joon-Sung (Department of Semiconductor Systems Engineering, Sungkyunkwan University)
  • Published : 2016.06.01
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Abstract

System-on-chip (SoC) designs have a number of flip-flops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.

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References

  1. K.O. Boateng, H. Kawasaki, and T. Nakata, "A Method of Static Compaction of Test Stimuli," Asian Test Symp., Kyoto, Japan, Nov. 19-21, 2001, pp. 137-142.
  2. I. Pomeranz, "Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests," IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst., vol. 33, no. 12, Dec. 2014, pp. 1955-1964. https://doi.org/10.1109/TCAD.2014.2358932
  3. B. Ayari and B. Kaminska, "A New Dynamic Test Vector Compaction for Automatic Test Pattern Generation," IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst., vol. 13, no. 3, Mar. 1994, pp. 353-358. https://doi.org/10.1109/43.265676
  4. S. Neophytou, S. Hadjitheophanous, and M.K. Michael, "On the Impact of Fault List Partitioning in Parallel Implementations for Dynamic Test Compaction Considering Multicore Systems," Int. Des.Test Symp., Marrakech, Morocco, Dec. 16-18, 2013, pp. 1-6.
  5. S.N. Neophytou and M.K. Michael, "Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques," IEEE Trans. Comput., vol. 59, no. 3, Mar. 2010, pp. 301-316. https://doi.org/10.1109/TC.2009.178
  6. N.A. Touba, "Survey of Test Vector Compression Techniques," IEEE Des. Test Comput., vol. 23, no. 4, Apr. 2006, pp. 294-303. https://doi.org/10.1109/MDT.2006.105
  7. M. Chloupek, O. Novak, and J. Jenicek, "On Test Time Reduction Using Pattern Overlapping, Broadcasting and on-Chip Decompression," IEEE Int. Symp. Des. Diagnostics Electron. Circuits Syst., Tallinn, Estonia, Apr. 18-20, 2012, pp. 300-305.
  8. P. Gupta, A.B. Kahng, and S. Mantik, "Routing-Aware Scan Chain Ordering," Asian South Pacific Des. Autom. Conf., Jan. 21-24, 2003, pp. 857-862.
  9. S. Banerjee et al., "Layout-Aware Illinois Scan Design for High Fault Coverage," Int. Symp. Quality Electron. Des., San Jose, CA, USA, Mar. 22-24, 2010, pp. 683-688.
  10. R. Lu et al., "Flip-Flop and Repeater Insertion for Early Interconnect Planning," Des. Autom. Test Europe Conf. Exhibition, Paris, France, Mar. 4-8, 2002, pp. 690-695.
  11. J. Xu, "Strategies of Handling Global Signals in Nanometer Integrated Circuits," M.S. thesis, Dept. Electr. Comput. Eng., University of Illinois, Chicago, USA, 2009.
  12. Synopsys IC Compiler Datasheet, Accessed Mar. 1, 2016. http://www.synopsys.com/Tools/Implementation/PhysicalImplementation/Documents/iccompiler_ds.pdf
  13. V. Jain and I. Waicukauski, "Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique," Proc. Int. Test Conf., Oct. 2002, pp. 148-153.
  14. L.T. Wang et al., "VirtualScan: A New Compressed Scan Technology for Test Cost Reduction," Proc. Int. Test Conf., Oct. 26-28, 2004, pp. 916-925.
  15. P.C. Tsai and S.J. Wang, "Multi-mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction," IET Comput. Digit. Techn., vol. 2, no. 6, Nov. 2008, pp. 434-444. https://doi.org/10.1049/iet-cdt:20070115