Journal of Electrical Engineering and Technology

The Korean Institute of Electrical Engineers (대한전기학회)
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FPGA Implementation of Diode Clamped Multilevel Inverter for Speed Control of Induction Motor

  • Kuppuswamy, C.L. (Satyabhama University) ;
  • Raghavendiran, T.A. (Satyabhama University)
  • Received : 2017.08.23
  • Accepted : 2017.10.24
  • Published : 2018.01.01
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Abstract

This work proposes FPGA implementation of Carrier Disposition PWM for closed loop seven level diode clamped multilevel inverter in speed control of induction motor. VLSI architecture for carrier Disposition have been introduced through which PWM signals are fed to the neutral point seven level diode clamped multilevel using which the speed of the induction motor is controlled. This proposed VLSI architecture makes the power circuit to work better with reduced stresses across the switches and a very low voltage and current total harmonic distortion (THD). The output voltages, currents, torque & speed characteristics for seven level neutral point diode clamped multilevel inverter for AC drive was studied. It has observed the proposed scheme introduces less distortion and harmonics. The results were validated using real time results.

Keywords

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Fig. 1. Three phase seven level diode clamped inverter

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Fig. 2. Non shoot through mode equivalent circuit

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Fig. 3. Shoot through mode equivalent circuit

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Fig. 4. Phase disposition PWM

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Fig. 5. Phase opposite disposition PWM

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Fig. 6. Phase shifted carrier control technique

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Fig. 7. Simulation of seven level diode clamped multilevelinverter

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Fig. 8. Third harmonic injected reference waveform

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Fig. 9. Stator current for phase disposition carrier PWM

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Fig. 10. Line to line voltage for in phase disposition carrierPWM

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Fig. 11. Phase voltage for phase disposition carrier PWM

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Fig. 12. Various THD measured during simulation for PD PWM technique. (a) Line to line voltage THD (b) Phase voltage THD (c) Stator current THD

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Fig. 13. Reference and actual speed

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Fig. 14. Proposed Sequential Architecture for PDPWM

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Fig. 15. FPGA architecture for Carrier frequency samplingmodule

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Fig. 16. FPGA architecture for Reference carrier generationmodule

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Fig. 17. Phase comparison module

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Fig. 18. FPGA Carrier Pulse for PD PWM using Modelsim

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Fig. 19. FPGA carrier pulse reference waveform for PDPWM using modelsim

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Fig. 20. FPGA Carrier ？ Reference Generation PD PWMusing Modelsim

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Fig. 21. FPGA PWM generation PD PWM using Modelsim

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Fig. 22. FPGA Reference PD PWM using Modelsim

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Fig. 23. Proposed hardware for Speed control of inductionmotor using PDPWM implemented on FPGA

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Fig. 24. Wiring diagram for Diode Clamped seven levelInverter ？ one leg

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Fig. 25. Power supply unit for Diode Clamped seven levelInverter ？ one leg

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Fig. 26. Proposed hardware circuit set up

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Fig. 27. PWM pulse generated from FPGA displayed in DSO

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Fig. 28. Current THD measured using THD meter

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Fig. 29. Voltage THD measured using THD meter

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Fig. 30. Phase voltage THD measured using THD meter

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Fig. 31. Phase current THD measured using THD meter

Table 1. Switch states for three phase seven level diode clamped inverter

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Table 2. Comparison of different measures on various PWM techniques on seven level diode clamped multilevel inverter

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Table 3. Parameters used of power circuit used for simulation

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Table 4. Comparison of simulated and actual quantitative parameters of the proposed hardware circuit

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