Journal of Power Electronics

The Korean Institute of Power Electronics (전력전자학회)
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A Generalized Space Vector Modulation Scheme Based on a Switch Matrix for Cascaded H-Bridge Multilevel Inverters

  • K.J., Pratheesh (Department of Electrical Engineering, National Institute of Technology) ;
  • G., Jagadanand (Department of Electrical Engineering, National Institute of Technology) ;
  • Ramchand, Rijil (Department of Electrical Engineering, National Institute of Technology)
  • Received : 2017.07.25
  • Accepted : 2017.11.01
  • Published : 2018.03.20
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Abstract

The cascaded H Bridge (CHB) multilevel inverter (MLI) is popular among the classical MLI topologies due to its modularity and reliability. Although space vector modulation (SVM) is the most suitable modulation scheme for MLIs, it has not been used widely in industry due to the higher complexity involved in its implementation. In this paper, a simple and novel generalized SVM algorithm is proposed, which has both reduced time and space complexity. The proposed SVM involves the generalization of both the duty cycle calculation and switching sequence generation for any n-level inverter. In order to generate the gate pulses for an inverter, a generalized switch matrix (SM) for the CHB inverter is also introduced, which further simplifies the algorithm. The algorithm is tested and verified for three-phase, three-level and five-level CHB inverters in simulations and hardware implementation. A comparison of the proposed method with existing SVM schemes shows the superiority of the proposed scheme.

Keywords

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Fig. 1. Space vector diagram of a three-level inverter.

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Fig. 2. Switching sequence in space vector modulation:(a)ascending; (b) descending.

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Fig. 3. Switching sequence in nearest level modulation: (a)ascending; (b) descending.

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Fig. 4. Sub-hexagon centres in a space vector diagram of a threelevel inverter.

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Fig. 5. Dmax, Dmid and Dmin variation.

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Fig. 6. SVM duty cycles using the proposed method.

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Fig. 7. Switch numbering followed for each H-bridge of theinverter. For additional H-bridges in the same phase (leg) thenumbering is continuous.

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Fig. 8. Complete flowchart for the proposed SVM scheme.

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Fig. 9. Switching functions of: (a) five-level; (b) seven-level; (c) nine-level; (d) 21 level inverter.

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Fig. 10. Pole voltages of CHB inverters at a modulation index of 0.85: (a) three-level; (b) five-level.

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Fig. 11. Line voltages of CHB inverters, at a modulation index of 0.85: (a) three-level; (b) five-level.

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Fig. 12. Photograph of the experimental setup.

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Fig. 13. Experimental results in a three-level CHBI for: (a) pole voltages; (b) line voltages; (c) phase voltages.

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Fig. 14. Experimental results in a five-level CHBI for: (a) pole voltages; (b) line voltages; (c) phase voltages.

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Fig. 15. Experimental results for phase voltage (CH1) and its corresponding phase current (CH2) for: (a) three-level CHBI; (b) five-levelCHBI; and (c) variation inthe pole voltage of a five-level CHB inverter while the modulation index is varied from 0.2 to 0.9.

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Fig. 16. Experimental results of line voltage THD vs. modulationindex.

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Fig. 17. Comparison of the dynamic load response of theproposed switch matrix based SVM (SM SVM) and thetwo-level inverter based SVM (TI SVM) in [21]: (a) Statorcurrent comparison; (b) Speed comparison.

TABLE I DUTY RATIO CLASSIFICATION

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TABLE II SWITCHING SEQUENCE DESIGN USING A SEQUENCE SELECTOR

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TABLE III SWITCHING FUNCTION VALUES AND SWITCH CONDITIONS

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TABLE IV SIMULATION AND EXPERIMENTAL PARAMETERS

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TABLE V COMPARISON OF THE TIMER TASK TURNAROUND TIME

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TABLE VI COMPARISON OF THE MEMORY REQUIREMENT

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TABLE VII COMPARISON OF LINE VOLTAGE THD

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