마이크로전자및패키징학회지 (Journal of the Microelectronics and Packaging Society)

  • 제26권1호
  • /
  • Pages.29-33
  • /
  • 2019
  • /
  • 1226-9360(pISSN)
  • /
  • 2287-7525(eISSN)
한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
권호 표지
DOI QR코드

DOI QR Code

팬아웃 웨이퍼 레벨 패키지 공정 중 재료 물성의 불확실성이 휨 현상에 미치는 영향

Effect of Material Property Uncertainty on Warpage during Fan Out Wafer-Level Packaging Process

  • 김금택 (울산과학기술원 기계항공 및 원자력 공학부) ;
  • 강기훈 (울산과학기술원 기계항공 및 원자력 공학부) ;
  • 권대일 (건국대학교 기계공학부)
  • Kim, Geumtaek (School of Mechanical, Aerospace and Nuclear Engineering, UNIST) ;
  • Kang, Gihoon (School of Mechanical, Aerospace and Nuclear Engineering, UNIST) ;
  • Kwon, Daeil (Department of Mechanical Engineering, Konkuk University)
  • 투고 : 2019.03.04
  • 심사 : 2019.03.29
  • 발행 : 2019.03.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

전자패키지 크기의 소형화와 전자기기의 성능 향상이 함께 이루어지면서 높은 입출력 밀도 구현이 중요한 요소로서 평가받고 있다. 이를 구현하기 위해 팬아웃 웨이퍼 레벨 패키지(FO-WLP)가 큰 주목을 받고 있다. 하지만 FO-WLP는 휨(Warpage) 현상에 취약하다는 약점이 있다. 휨 현상은 생산 수율 감소와 더불어 패키지 신뢰성 하락에 큰 원인이므로 이를 최소화하는 것이 필수적이다. 유한요소해석을 이용한 재질의 물성 등 FO-WLP의 휨 현상과 연관된 요소에 대한 많은 연구가 진행되어 왔지만, 대부분의 연구는 이러한 요소들의 불확실성을 고려하지 않았다. 재질의 물성, 칩의 위치 등 패키지의 휨 현상과 연관된 요소들은 제조 측면에서 보았을 때 불확실성을 가지고 있기 때문에, 실제 결과와 더 가깝게 모사하기 위해서는 이러한 요소들의 불확실성이 고려되어야 한다. 이번 연구에서는 FO-WLP 과정 중 칩의 탄성 계수가 정규 분포를 따르는 불확실성을 가졌을 때 휨 현상에 미치는 영향을 유한요소해석을 통해 알아보았다. 그 결과 칩의 탄성 계수의 불확실성이 최대 von Mises 응력에 영향을 미치는 것을 확인하였다. Von Mises 응력은 전체 패키지 신뢰성과 관련된 인자이기 때문에 칩의 물성에 대한 불확실성 제어가 필요하다.

With shrinking form factor and improving performance of electronic packages, high input/output (I/O) density is considered as an important factor. Fan out wafer-level packaging (FO-WLP) has been paid great attention as an alternative. However, FO-WLP is vulnerable to warpage during its manufacturing process. Minimizing warpage is essential for controlling production yield, and in turn, package reliability. While many studies investigated the effect of process and design parameters on warpage using finite element analysis, they did not take uncertainty into consideration. As parameters, including material properties, chip positions, have uncertainty from the point of manufacturing view, the uncertainty should be considered to reduce the gap between the results from the field and the finite element analysis. This paper focuses on the effect of uncertainty of Young's modulus of chip on fan-out wafer level packaging warpage using finite element analysis. It is assumed that Young's modulus of each chip follows the normal distribution. Simulation results show that the uncertainty of Young's modulus affects the maximum von Mises stress. As a result, it is necessary to control the uncertainty of Young's modulus of silicon chip since the maximum von Mises stress is a parameter related to the package reliability.

키워드

MOKRBW_2019_v26n1_29_f0001.png 이미지

Fig. 1. Process flow for chip first FO-WLP.

MOKRBW_2019_v26n1_29_f0002.png 이미지

Fig. 2. Model structure.

MOKRBW_2019_v26n1_29_f0003.png 이미지

Fig. 3. Finite element model (quarter model).

MOKRBW_2019_v26n1_29_f0004.png 이미지

Fig. 4. Normalized maximum warpage (maximum deformation).

MOKRBW_2019_v26n1_29_f0005.png 이미지

Fig. 5. maximum von Mises stress.

MOKRBW_2019_v26n1_29_f0006.png 이미지

Fig. 6. Stress contour for one of simulations in case 4.

MOKRBW_2019_v26n1_29_f0007.png 이미지

Fig. 7. Relationship among Young’s Modulus, von Mises stress and the distance from the wafer center.

Table 1. Material properties used in finite element analysis

MOKRBW_2019_v26n1_29_t0001.png 이미지

Table 2. Material properties of silicon

MOKRBW_2019_v26n1_29_t0002.png 이미지

Table 3. Summary of simulation results of warpage

MOKRBW_2019_v26n1_29_t0003.png 이미지

Table 4. Summary of simulation results of von Mises stress

MOKRBW_2019_v26n1_29_t0004.png 이미지

참고문헌

  1. M. Brunnbauer, E. Furgut, G. Beer, and T. Meyer, "Embedded wafer level ball grid array (eWLB)", Proc. 8th Electronics Packaging Technology Conference, 1, IEEE (2006).
  2. S. C. Chong, C. H. Khong, K. L. C. Sing, D. H. S. Wee, C. T. W. Liang, V. L. W. Sheng, K. H. Joon, J. Lee, and V. S. Rao, "Process challenges and development of eWLP", Proc. 12th Electronics Packaging Technology Conference, 527, IEEE (2010).
  3. S. Shin, M. Park, S. E. Kim, and S. Kim, "Effects of Wafer Warpage on the Misalignment in Wafer Level Stacking Process", J. Microelectron. Packag. Soc., 20(3), 71 (2013). https://doi.org/10.6117/kmeps.2013.20.3.071
  4. J. Lau, "Warpage Issues in Fan-Out Wafer Level Packaging" 3DInCites, (Jun. 26, 2017) from https://www.3dincites.com/
  5. M. K. Lee, J. W. Jeoung, J. Y. Ock, and S.-H. Choa, "Numerical Analysis of Warpage and Reliability of Fan-out Wafer Level Package", J. Microelectron. Packag. Soc., 21(1), 31 (2014). https://doi.org/10.6117/kmeps.2014.21.1.031
  6. G. T. Kim and D. Kwon, "Warpage Analysis during Fan-Out Wafer Level Packaging Process using Finite Element Analysis", J. Microelectron. Packag. Soc., 25(1), 41 (2018). https://doi.org/10.6117/KMEPS.2018.25.1.041
  7. J. H. Lau, M. Li, D. Tian, N. Fan, E. Kuah, W. Kai, M. Li, J. Hao, Y. M. Cheung, and Z. Li, "Warpage and thermal characterization of fan-out wafer-level packaging", IEEE Transactions on Components, Packaging Manufacturing Technology, 7(10), 1729 (2017). https://doi.org/10.1109/TCPMT.2017.2715185
  8. A. Salahouelhadj, M. Gonzalez, A. Podpod, K. Rebibis, and E. Beyne, "Study of the influence of material properties and geometric parameters on warpage for Fan-Out Wafer Level Packaging", Proc. 7th Electronic System-Integration Technology Conference (ESTC), 1, IEEE (2018).
  9. P. B. Lin, C.-T. Ko, W.-T. Ho, C.-H. Kuo, K.-W. Chen, Y.-H. Chen, and T.-J. Tseng, "A Comprehensive Study on Stress and Warpage by Design, Simulation and Fabrication of RDLFirst Panel Level Fan-Out Technology for Advanced Package", Proc. 67th Electronic Components and Technology Conference (ECTC), 1413, IEEE (2017).
  10. S.-S. Deng, S.-J. Hwang, and H.-H. Lee, "Warpage prediction and experiments of fan-out waferlevel package during encapsulation process", IEEE Transactions on Components, Packaging Manufacturing Technology, 3(3), 452 (2013). https://doi.org/10.1109/TCPMT.2012.2228005
  11. T.-C. Chiu and E.-Y. Yeh, "Warpage simulation for the reconstituted wafer used in fan-out wafer level packaging", Microelectronics Reliability, 80, 14 (2018). https://doi.org/10.1016/j.microrel.2017.11.008
  12. D. Moens and M. Hanss, "Non-probabilistic finite element analysis for parametric uncertainty treatment in applied mechanics: Recent advances", Finite Elements in Analysis Design, 47(1), 4 (2011). https://doi.org/10.1016/j.finel.2010.07.010
  13. C. Wang, Z. Qiu, and Y. Li, "Hybrid uncertainty propagation of coupled structural-acoustic system with large fuzzy and interval parameters", Applied Acoustics, 102, 62 (2016). https://doi.org/10.1016/j.apacoust.2015.09.006
  14. H. Turnbull and P. Omenzetter, "Comparison of two optimization algorithms for fuzzy finite element model updating for damage detection in a wind turbine blade", in Nondestructive Characterization and Monitoring of Advanced Materials, Aerospace, Civil Infrastructure, and Transportation XII, 10599, 105991Q, International Society for Optics and Photonics (2018).
  15. F. Lara-Molina, E. Koroishi, and V. Steffen, "Uncertainty analysis of a two-link robot manipulator under fuzzy parameters", Proc. Joint Conference on Robotics: SBR-LARS Robotics Symposium and Robocontrol, 1, IEEE (2014).
  16. J. H. Lau, N. Fan, and M. Li, "Design, material, process, and equipment of embedded fan-out wafer/panel-level packaging", Chip Scale Review, 20(3), 38 (2016).
  17. F. X. Che, D. Ho, M. Z. Ding, and X. Zhang, "Modeling and design solutions to overcome warpage challenge for fan-out wafer level packaging (FO-WLP) technology", Proc. 17th Electronics Packaging and Technology Conference, 1, IEEE (2015).

피인용 문헌

  1. MLCC Solder Joint Property with Vacuum and Hot Air Reflow Soldering Processes vol.39, pp.4, 2019, https://doi.org/10.5781/jwj.2021.39.4.2
  2. Laser Soldering Properties of MEMS Probe for Semiconductor Water Testing vol.39, pp.4, 2019, https://doi.org/10.5781/jwj.2021.39.4.4