The Journal of Korean Institute of Electromagnetic Engineering and Science (한국전자파학회논문지)

The Korean Institute of Electromagnetic Engineering and Science (한국전자파학회)
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High-Efficiency CMOS Power Amplifier using Low-Loss PCB Balun with Second Harmonic Impedance Matching

2차 고조파 정합 네트워크를 포함하는 저손실 PCB 발룬을 이용한 고효율 CMOS 전력증폭기

  • Kim, Hyungyu (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lim, Wonseob (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kang, Hyunuk (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Wooseok (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Oh, Sungjae (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Oh, Hansik (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Yang, Youngoo (School of Information and Communication Engineering, Sungkyunkwan University)
  • 김현규 (성균관대학교 정보통신대학) ;
  • 임원섭 (성균관대학교 정보통신대학) ;
  • 강현욱 (성균관대학교 정보통신대학) ;
  • 이우석 (성균관대학교 정보통신대학) ;
  • 오성재 (성균관대학교 정보통신대학) ;
  • 오한식 (성균관대학교 정보통신대학) ;
  • 양영구 (성균관대학교 정보통신대학)
  • Received : 2018.10.26
  • Accepted : 2019.01.04
  • Published : 2019.02.28
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Abstract

In this paper, a complementary metal oxide semiconductor(CMOS) power amplifier(PA) integrated circuit operating in the 900 MHz band for long-term evolution(LTE) communication systems is presented. The output matching network based on a transformer was implemented on a printed circuit board for low loss. Simultaneously, to achieve high efficiency of the PA, the second harmonic impedances are controlled. The CMOS PA was fabricated using a $0.18{\mu}m$ CMOS process and measured using an LTE uplink signal with a bandwidth of 10 MHz and peak to average power ratio of 7.2 dB for verification. The implemented CMOS PA module exhibits a power gain of 24.4 dB, power-added efficiency of 34.2%, and an adjacent channel leakage ratio of -30.1 dBc at an average output power level of 24.3 dBm.

본 논문에서는 long term evolution(LTE) 통신을 위한 900 MHz 대역에서 동작하는 CMOS 전력증폭기 집적회로 설계 결과를 제시한다. 출력단에서의 적은 손실을 위해 트랜스포머를 이용한 출력 정합 회로가 printed circuit board(PCB) 상에 구현되었다. 동시에, 2차 고조파 임피던스의 조정을 통해 전력증폭기의 고효율 동작을 달성하였다. 전력증폭기는 $0.18{\mu}m$ CMOS 공정을 이용하여 설계되었으며, 10 MHz의 대역폭 및 7.2 dB 첨두 전력 대 평균 전력비(PAPR)의 특성을 갖는 LTE up-link 신호를 이용하여 측정되었다. 제작된 전력증폭기 모듈은 평균 전력 24.3 dBm에서 34.2 %의 전력부가효율(PAE) 및 -30.1 dBc의 인접 채널 누설비(ACLR), 그리고 24.4 dB의 전력 이득을 갖는다.

Keywords

JJPHCH_2019_v30n2_104_f0001.png 이미지

그림 1. 설계된 CMOS 전력증폭기의 회로도 Fig. 1. Schematic diagram of the designed CMOS PA.

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그림 3. 주 증폭단 드레인 2차 고조파 임피던스 정합 유무에 따른 성능 비교 Fig. 3. Performance comparisons with respect to 2nd harmonic impedance matching at the drain of the main stage.

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그림 4. 주 증폭단 드레인 임피던스 정합 네트워크 Fig. 4. Impedance matching network at the drain of the main stage.

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그림 5. 주 증폭단의 2차 고조파 임피던스 Fig. 5. Second harmonic impedances of the main stage.

JJPHCH_2019_v30n2_104_f0006.png 이미지

그림 6. 제작된 전력증폭기 Fig. 6. Photographs of the implemented CMOS PA.

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그림 7. 시뮬레이션 결과 및 측정된 산란 계수 Fig. 7. Simulated and measured S-parameters.

JJPHCH_2019_v30n2_104_f0008.png 이미지

그림 8. CMOS 전력증폭기의 측정된 성능 Fig. 8. Measured performances of the CMOS PA.

JJPHCH_2019_v30n2_104_f0009.png 이미지

그림 2. 주 증폭단 소스 2차 고조파 임피던스 정합 네트워크 Fig. 2. Second harmonic impedance matching network at the source of the main stage.

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