Fig. 1. Architecture of SSD
Fig. 2. Architecture of CLOCK-HBM
Fig. 3. The detailed diagram for the state of pages inCLOCK-HBM
Fig. 4. The normalized number of swapping operations in hybrid buffer
Fig. 5. The number of write operations in hybrid buffer
Fig. 6. The number of read operations in hybrid buffer
Table 1. Characteristics of memories
Table 2. Switching conditions for the number of write operations of each level in DRAM buffer page
Table 3. Parameters for SSD model in the simulator
Table 4. Detailed characteristics of workloads
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