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Compact Hardware Multiple Input Multiple Output Channel Emulator for Wireless Local Area Network 802.11ac

  • Khai, Lam Duc (Department of Computer Engineering, University of Information Technology) ;
  • Tien, Tran Van (Department of Computer Engineering, University of Information Technology)
  • Received : 2019.07.19
  • Accepted : 2020.03.06
  • Published : 2020.03.31

Abstract

This paper proposes a fast-processing and low-cost hardware multiple input multiple output (MIMO) channel emulator. The channel emulator is an important component of hardware-based simulation systems. The novelty of this work is the use of sharing and pipelining functions to reduce hardware resource utilization while maintaining a high sample rate. In our proposed emulator, the samples are created sequentially and interpolated to ensure the sample rate is equal to the base band rate. The proposed 4 × 4 MIMO requires low-cost hardware resource so that it can be implemented on a single field-programmable gate array (FPGA) chip. An implementation on Xilinx Virtex-7 VX980T was found to occupy 10.47% of the available configurable slice registers and 12.58% of the FPGA's slice lookup tables. The maximum frequency of the proposed emulator is 758.064 MHz, so up to 560 different paths can be processed simultaneously to generate 560 × 758 million × 2 × 32 bit complex-valued fading samples per second.

Keywords

References

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