DOI QR코드

DOI QR Code

Review of Injection-Locked Oscillators

  • Choo, Min-Seong (Center for Nanotechnology, NASA Ames Research Center) ;
  • Jeong, Deog-Kyoon (Department of Electrical and Computer Engineering, Seoul National University)
  • Received : 2020.06.02
  • Accepted : 2020.06.15
  • Published : 2020.06.30

Abstract

Handling precise timing in high-speed transceivers has always been a primary design target to achieve better performance. Many different approaches have been tried, and one of those is utilizing the beneficial nature of injection locking. Though the phenomenon was not intended for building integrated circuits at first, its coupling effect between neighboring oscillators has been utilized deliberately. Consequently, the dynamics of the injection-locked oscillator (ILO) have been explored, starting from R. Adler. As many aspects of the ILO were revealed, further studies followed to utilize the technique in practice, suggesting alternatives to the conventional frequency syntheses, which tend to be complicated and expensive. In this review, the historical analysis techniques from R. Adler are studied for better comprehension with proper notation of the variables, resulting in numerical results. In addition, how the timing jitter or phase noise in the ILO is attenuated from noise sources is presented in contrast to the clock generators based on the phase-locked loop (PLL). Although the ILO is very promising with higher cost effectiveness and better noise immunity than other schemes, unless correctly controlled or tuned, the promises above might not be realized. In order to present the favorable conditions, several strategies have been explored in diverse applications like frequency multiplication, data recovery, frequency division, clock distribution, etc. This paper reviews those research results for clock multiplication and data recovery in detail with their advantages and disadvantages they are referring to. Through this review, the readers will hopefully grasp the overall insight of the ILO, as well as its practical issues, in order to incorporate it on silicon successfully.

Keywords

References

  1. R. Adler, "A Study of Locking Phenomena in Oscillators," Proceedings of the IRE, vol. 34, no. 6, pp. 351-357, June 1946. https://doi.org/10.1109/JRPROC.1946.229930
  2. K. Kurokawa, "Noise in Synchronized Oscillators," IEEE Trans. Microw. Theory Tech., vol. 16, no. 4, pp. 234-240, Apr. 1968. https://doi.org/10.1109/TMTT.1968.1126656
  3. X. Zhang, X. Zhou, and A. S. Daryoush, "A theoretical and experimental study of the noise behavior of subharmonically injection locked local oscillators," IEEE Trans. Microw. Theory Tech., vol. 40, no. 5, pp. 895-902, May 1992. https://doi.org/10.1109/22.137395
  4. S. Ye, L. Jansson, and I. Galton, "A multiple-crystal interface PLL with VCO realignment to reduce phase noise," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1795-1803, Dec. 2002. https://doi.org/10.1109/JSSC.2002.804339
  5. B. Razavi, "A study of injection locking and pulling in oscillators," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sept. 2004. https://doi.org/10.1109/JSSC.2004.831608
  6. A. Mirzaei, M. E. Heidari, R. Bagheri, S. Chehrazi, and A. A. Abidi, "The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking," IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1916-1932, Sept. 2007. https://doi.org/10.1109/JSSC.2007.903047
  7. J. Lee and H. Wang, "Study of Subharmonically Injection-Locked PLLs," IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1539-1553, May 2009. https://doi.org/10.1109/JSSC.2009.2016701
  8. M. Farazian, P. S. Gudem, and L. E. Larson, "Stability and Operation of Injection-Locked Regenerative Frequency Dividers," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 8, pp. 2006-2019, 2010. https://doi.org/10.1109/TCSI.2010.2043012
  9. D. Dunwell and A. C. Carusone, "Modeling Oscillator Injec-tion Locking Using the Phase Domain Response," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 11, pp. 2823-2833, Nov. 2013. https://doi.org/10.1109/TCSI.2013.2252654
  10. N. D. Dalt, "An Analysis of Phase Noise in Realigned VCOs," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 3, pp. 143-147, Mar. 2014. https://doi.org/10.1109/TCSII.2013.2296195
  11. B. M. Helal, C.-M. Hsu, K. Johnson, and M. H. Perrott, "A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop," IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1391-1400, May 2009. https://doi.org/10.1109/JSSC.2009.2015816
  12. E. Monaco, M. Pozzoni, F. Svelto, and A. Mazzanti, "Injection-Locked CMOS Frequency Doublers ${\mu}$-Wave and mm-Wave Applications," IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1565-1574, Aug. 2010. https://doi.org/10.1109/JSSC.2010.2049780
  13. Y.-C. Huang and S.-I. Liu, "A 2.4-GHz Subharmonically In-jection-Locked PLL With Self-Calibrated Injection Timing," IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 417-428, Feb. 2013. https://doi.org/10.1109/JSSC.2012.2227609
  14. I.-T. Lee et al., "A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing," in ISSCC, Dig. Tech. Papers, Feb.2013, pp. 414-415.
  15. A. Musa et al., "A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration," IEEE J. Solid-State Circuits, vol. 49, no. 1, pp. 50-60, Jan. 2014. https://doi.org/10.1109/JSSC.2013.2284651
  16. J.-C. Chien et al., "A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS," in ISSCC, Dig. Tech. Papers, Feb. 2014, pp. 52-53.
  17. A. Li, S. Zheng, J. Yin, X. Luo, and H. C. Luong, "A 21-48 GHz Subharmonic Injection-Locked Fractional-N Frequency Synthesizer for Multiband Point-to-Point Backhaul Commu-nications," IEEE J. Solid-State Circuits, vol. 49, no. 8, pp. 1785-1799, Aug. 2014. https://doi.org/10.1109/JSSC.2014.2320952
  18. W. Deng et al., "A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injec-tion Technique," IEEE J. Solid-State Circuits, vol. 50, no. 1, pp. 68-80, Jan. 2015. https://doi.org/10.1109/JSSC.2014.2348311
  19. C.-L. Wei, T.-K. Kuan, and S.-I. Liu, "A Subharmonically In-jection-Locked PLL With Calibrated Injection Pulsewidth," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 62, no. 6, pp. 548-552, June 2015. https://doi.org/10.1109/TCSII.2015.2407753
  20. A. Elkholy, M. Talegaonkar, T. Anand, and P. K. Hanumolu, "Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers," IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 3160-3174, Dec. 2015. https://doi.org/10.1109/JSSC.2015.2478449
  21. S. Choi, S. Yoo, Y. Lim, and J. Choi, "A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multi-plier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector," IEEE J. Solid-State Circuits, vol. 51, no. 8, pp. 1878-1889, Aug. 2016. https://doi.org/10.1109/JSSC.2016.2574804
  22. S. Kim et al., "A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration," in ISSCC, Dig. Tech. Papers, Feb. 2017, pp. 494-495.
  23. H. C. Ngo et al., "A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO," in ISSCC, Dig. Tech. Papers, Feb. 2017, pp. 150-151.
  24. D. Coombs, A. Elkholy, R. K. Nandwana, A. Elmallah, and P. K. Hanumolu, "A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cas-caded ring-based digital injection-locked clock multiplier in 65nm CMOS," in ISSCC, Dig. Tech. Papers, Feb. 2017, pp. 152-153.
  25. S.-Y. Cho et al., "A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 9, pp. 2691-2702,Sep. 2018. https://doi.org/10.1109/TCSI.2018.2799195
  26. M.-S. Choo, H.-G. Ko, S.-Y. Cho, K. Lee, and D.-K. Jeong, "An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 12, pp. 1819-1823, Dec. 2018. https://doi.org/10.1109/TCSII.2018.2878565
  27. M.-S. Choo et al., "A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Ad-justment of Phase Domain Response," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 66, no. 12, pp. 1932-1936, Dec. 2019. https://doi.org/10.1109/TCSII.2019.2949555
  28. D. Liao, Y. Zhang, F. F. Dai, Z. Chen, and Y. Wang, "An mm-Wave Synthesizer With Robust Locking Reference-Sam-pling PLL and Wide-Range Injection-Locked VCO," IEEE J. Solid-State Circuits, vol. 55, no. 3, pp. 536-546, Mar. 2020. https://doi.org/10.1109/jssc.2019.2959513
  29. J. Zhang et al., "A 21.7-to-41.7-GHz Injection-Locked LO Generation With a Narrowband Low-Frequency Input for Multiband 5G Communications," IEEE Trans. Microw. Theory Tech., vol. 68, no. 1, pp. 170-183, Jan. 2020. https://doi.org/10.1109/tmtt.2019.2940024
  30. H.-T. Ng et al., "A second-order semidigital clock recovery circuit based on injection locking," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp.2101-2110, Dec. 2003. https://doi.org/10.1109/JSSC.2003.818576
  31. J.-B. Begueret, Y. Deval, C. Scarabello, J.-Y. L. Gall, and M. Pignol, "An innovative open-loop CDR based on injection-locked oscillator for high-speed data link applications," in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003, June 2003, pp. 313-316.
  32. M. Nogawa et al., "A 10 Gb/s burst-mode CDR IC in $0.13{\mu}m$ CMOS," in ISSCC, Dig. Tech. Papers, Feb. 2005, pp. 228-595.
  33. J.-H. C. Zhan, J. S. Duster, and K. T. Kornegay, "Full-rate in-jection-locked 10.3Gb/s clock and data recovery circuit in a 45GHz-fT SiGe process," in Proc. IEEE Custom Integr. Circuits Conf., Sept. 2005, pp. 552-555.
  34. J. Terada et al., "A 10.3125Gb/s Burst-Mode CDR Circuit us-ing a ${\Delta}{\Sigma}$ DAC," in ISSCC, Dig. Tech. Papers, Feb. 2008, pp. 226-609.
  35. J. Lee and M. Liu, "A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique," IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 619-630, Mar. 2008. https://doi.org/10.1109/JSSC.2007.916598
  36. K. Maruko et al., "A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator," in ISSCC, Dig. Tech. Papers, Feb. 2010, pp. 364-365.
  37. Y. Take, N. Miura, and T. Kuroda, "A 30 Gb/s/Link 2.2 Tb/s/$mm^2$ Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface," IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2552-2559,Nov. 2011. https://doi.org/10.1109/JSSC.2011.2164023
  38. W.-S. Choi, T. Anand, G. Shu, A. Elshazly, and P. K. Hanumolu, "A Burst-Mode Digital Receiver With Program-mable Input Jitter Filtering for Energy Proportional Links," IEEE J. Solid-State Circuits, vol. 50, no. 3, pp. 737-748, Mar. 2015. https://doi.org/10.1109/JSSC.2015.2390613
  39. T. Masuda et al., "A 12 Gb/s 0.9 mW/Gb/s Wide-Bandwidth Injection-Type CDR in 28 nm CMOS With Reference-Free Frequency Capture," IEEE J. Solid-State Circuits, vol. 51, no. 12, pp. 3204-3215, Dec. 2016. https://doi.org/10.1109/JSSC.2016.2594077
  40. M.-S. Choo et al., "A 10-Gb/s, 0.03-$mm^2$, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology," IEEE J. Solid-State Circuits, vol. 54, no. 10, pp. 2812-2822, Oct. 2019. https://doi.org/10.1109/jssc.2019.2917833
  41. L. Zhang, B. Ciftcioglu, M. Huang, and H. Wu, "Injection-Locked Clocking: A New GHz Clock Distribution Scheme," in IEEE Custom Integrated Circuits Conference 2006, Sept. 2006, pp. 785-788.
  42. M. Hossain and A. C. Carusone, "CMOS Oscillators for Clock Distribution and Injection-Locked Deskew," IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2138-2153, Aug. 2009. https://doi.org/10.1109/JSSC.2009.2022917
  43. M. Hossain and A. C. Carusone, "A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS," in ISSCC, Dig. Tech. Papers, Feb. 2010, pp. 158-159.
  44. S. Shekha et al., "Strong Injection Locking in Low-Q LC Os-cillators: Modeling and Application in a Forwarded-Clock I/O Receiver," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 8, pp. 1818-1829, Aug. 2009. https://doi.org/10.1109/TCSI.2009.2027509
  45. Y.-J. Kim, S.-H. Chung, and L.-S. Kim, "A Quarter-Rate For-warded Clock Receiver Based on ILO With Low Jitter Track-ing Bandwidth Variation Using Phase Shifting Phenomenon in 65 nm CMOS," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 8, pp. 2482-2490, Aug. 2014. https://doi.org/10.1109/TCSI.2014.2332262
  46. Y.-J. Kim, S.-H. Chung, K.-S. Ha, S.-J. Bae, and L.-S. Kim, "A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 10, pp. 2495-2503, Oct. 2015. https://doi.org/10.1109/TCSI.2015.2459557
  47. M. Raj, S. Saeedi, and A. Emami, "A Wideband Injection Locked Quadrature Clock Generation and Distribution Tech-nique for an Energy-Proportional 16-32 Gb/s Optical Receiver in 28 nm FDSOI CMOS," IEEE J. Solid-State Circuits, vol. 51, no. 10, pp. 2446-2462, Oct. 2016. https://doi.org/10.1109/JSSC.2016.2584643
  48. D. Kim et al., "A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx," IEEE J. Solid-State Circuits, vol. 55, no. 1, pp. 167-177, Jan. 2020. https://doi.org/10.1109/jssc.2019.2948806
  49. H. R. Rategh, H. Samavati, and T. H. Lee, "A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver," IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 780-787, May 2000. https://doi.org/10.1109/4.841507
  50. C.-Y. Wu and C.-Y. Yu, "Design and Analysis of a Millimeter-Wave Direct Injection-Locked Frequency Divider With Large Frequency Locking Range," IEEE Trans. Microw. Theory Tech., vol. 55, no. 8, pp. 1649-1658, Aug. 2007. https://doi.org/10.1109/TMTT.2007.902067
  51. J.-C. Chien and L.-H. Lu, "Analysis and Design of Wideband Injection-Locked Ring Oscillators With Multiple-Input Injection," IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1906-1915, Sept. 2007. https://doi.org/10.1109/JSSC.2007.903058
  52. T.-N. Luo, S.-Y. Bai, and Y.-J. E. Chen, "A 60-GHz $0.13-{\mu}m$ CMOS Divide-by-Three Frequency Divider," IEEE Trans. Mi-crow. TheoryTech., vol. 56, no. 11, pp. 2409-2415, Nov. 2008. https://doi.org/10.1109/TMTT.2008.2004895
  53. M.-W. Li, P.-C. Wang, T.-H. Huang, and H.-R. Chuang, "Low-Voltage, Wide-Locking-Range, Millimeter-Wave Divide-by-5 Injection-Locked Frequency Dividers," IEEE Trans. Microw. Theory Tech., vol. 60, no. 3,pp. 679-685, Mar. 2012. https://doi.org/10.1109/TMTT.2011.2180397
  54. Wolfram Research Inc., Mathematica 8.0, 2010. [Online]. Available: http://www.wolfram.com
  55. P. Virtanen et al., "SciPy 1.0: Fundamental Algorithms for Sci-entific Computing in Python," Nature Methods, vol. 17, pp. 261-272, 2020. https://doi.org/10.1038/s41592-019-0686-2
  56. D. Fischette, "First Time, Every Time - Practical Tips for Phase-Locked Loop Design," URL: http://www.delroy.com/PLL_dir/tutorial/PLL_tuto-rial_slides.pdf
  57. A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998. https://doi.org/10.1109/4.658619
  58. A. Hajimiri, S. Limotyrakis, and T. H. Lee, "Jitter and phase noise in ring oscillators," IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 790-804, June 1999. https://doi.org/10.1109/4.766813
  59. F. M. Gardner, "Charge-Pump Phase-Lock Loops," IEEE Transactions on Communications, vol. 28, no. 11, pp. 1849-1858, Nov. 1980. https://doi.org/10.1109/tcom.1980.1094619
  60. W. Bae and D.-K. Jeong, Analysis and Design of CMOS Clocking Circuits for Low Phase Noise. London, U.K.: Institution of Engineering and Technology, 2020.