Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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Thermal Warpage Behavior of Single-Side Polished Silicon Wafers

단면 연마된 실리콘 웨이퍼의 열에 의한 휨 거동

  • Kim, Junmo (Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST)) ;
  • Gu, Chang-Yeon (Department of Mechanical Engineering, Pohang University of Science and Technology (POSTECH)) ;
  • Kim, Taek-Soo (Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST))
  • Received : 2020.08.24
  • Accepted : 2020.09.30
  • Published : 2020.09.30
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Abstract

Complex warpage behavior of the electronic packages causes internal stress so many kinds of mechanical failure occur such as delamination or crack. Efforts to predict the warpage behavior accurately in order to prevent the decrease in yield have been approached from various aspects. For warpage prediction, silicon is generally treated as a homogeneous material, therefore it is described as showing no warpage behavior due to thermal loading. However, it was reported that warpage is actually caused by residual stress accumulated during grinding and polishing in order to make silicon wafer thinner, which make silicon wafer inhomogeneous through thickness direction. In this paper, warpage behavior of the single-side polished wafer at solder reflow temperature, the highest temperature in packaging processes, was measured using 3D digital image correlation (DIC) method. Mechanism was verified by measuring coefficient of thermal expansion (CTE) of both mirror-polished surface and rough surface.

반도체 패키지의 경박단소화로 인해 발생하는 복잡한 휨 거동은 내부 응력을 발생시켜 박리나 균열과 같은 다양한 기계적인 결함을 야기한다. 이에 따른 수율 감소를 막기 위해 휨 거동을 정확하게 예측하려는 노력은 다양한 측면에서 그 접근이 이루어지고 있다. 이 중 패키지를 구성하는 주 재료인 실리콘 웨이퍼는 일반적으로 균질한 물질로 취급되어 열에 의한 휨 거동은 전혀 없는 것으로 묘사된다. 그러나 실리콘을 얇게 가공하기 위해서 진행되는 그라인딩과 폴리싱에 의해 상온에서 휨이 발생한다는 사실이 보고되어 있고, 이는 표면에 형성되는 damage layer가 두께 방향으로 불균질함을 발생시키는 것으로부터 기인한다. 이에 본 논문에서는 반도체 패키징 공정 중 최고온 공정 과정인 solder reflow 온도에서 단면 연마된 웨이퍼가 나타내는 휨 거동을 측정하고, 이러한 휨 량이 나타나는 원인을 연마된 면과 그렇지 않은 면의 열팽창계수를 측정함으로써 밝혀내었다. 측정에는 미세 변형률과 형상이 모두 측정 가능한 3차원 디지털 이미지 상관법(Digital Image Correlation; DIC)을 이용하였다.

Keywords

References

  1. T. Yoon and T. S. Kim, "Thermo-Mechanical Reliability of TSV based 3D-IC (in Korean)", J. Microelectron. Packag. Soc., 24(1), 35 (2017). https://doi.org/10.6117/kmeps.2017.24.1.035
  2. L. Shi, L. Chen, D. W. Zhang, E. Liu, Q. Liu, and C. I. Chen, "Improvement of Thermo-Mechanical Reliability of Wafer- Level Chip Scale Packaging", Journal of Electronic Packaging, 140(1), 011002 (2018). https://doi.org/10.1115/1.4038245
  3. P. Chen, Z. Ji, Y. Liu, C. Wu, N. Ye, and H. Takiar, "Warpage Prediction Methodology of Extremely Thin Package", Proc. 67th Electronic Components and Technology Conference (ECTC), 2080, IEEE (2017).
  4. C. Kim, T. I. Lee, M. S. Kim, and T. S. Kim, "Mechanism of Warpage Orientation Rotation due to Viscoelastic Polymer Substrates During Thermal Processing", Microelectronics Reliability, 73, 136 (2017). https://doi.org/10.1016/j.microrel.2017.04.021
  5. C. Kim, T. I. Lee, M. S. Kim, and T. S. Kim, "Warpage Analysis of Electroplated Cu Films on Fiber-Reinforced Polymer Packaging Substrates", Polymers, 7(6), 985 (2014). https://doi.org/10.3390/polym7060985
  6. P. Y. Lin and S. Lee, "Warpage Modeling of Ultra-Thin Packages Based on Chemical Shrinkage and Cure-Dependent Viscoelasticity of Molded Underfill", IEEE Transactions on Device and Materials Reliability, 20(1), 67 (2019). https://doi.org/10.1109/tdmr.2019.2956646
  7. J. B. Pyo, T. I. Lee, C. Kim, M. S. Kim, and T. S. Kim, "Prediction of Time-Dependent Swelling of Flexible Polymer Substrates Using Hygro-Mechanical Finite Element Simulations", Soft matter, 12(18), 4135 (2016). https://doi.org/10.1039/C5SM03109E
  8. T. I. Lee, C. Kim, J. B. Pyo, M. S. Kim and T. S. Kim, "Effect of Anisotropic Thermo-Elastic Properties of Woven-Fabric Laminates on Diagonal Warpage of Thin Package Substrates", Composites Structures, 176, 973 (2017). https://doi.org/10.1016/j.compstruct.2017.06.014
  9. A. V. Mazur and M. M. Gasik, "Thermal Expansion of Silicon at Temperatures up to 1100 C", Journal of materials processing technology, 209(2), 723 (2009). https://doi.org/10.1016/j.jmatprotec.2008.02.041
  10. S. Lee, J. H. Kim, Y. S. Kim, T. Ohba, and T. S. Kim, "Effects of Thickness and Crystallographic Orientation on Tensile Properties of Thinned Silicon Wafers", IEEE Transactions on Components, Packaging and Manufacturing Technology, 10(2), 296 (2019). https://doi.org/10.1109/tcpmt.2019.2931640
  11. S. Gao, Z. Dong, R. Kang, B. Zhang, and D. Guo, "Warping of Silicon Wafers Subjected to Back-Grinding Process", Precision Engineering, 40, 87 (2015). https://doi.org/10.1016/j.precisioneng.2014.10.009
  12. H. Shimizu, T. Watanabe, and Y. Kakui, "Warpage of Czochralski- Grown Silicon Wafers as Affected by Oxygen Precipitation", Japanese journal of applied physics, 24(7R), 815 (1985). https://doi.org/10.1143/JJAP.24.815
  13. S. Cho and S. E. Kim, "Effect of Si Grinding on Electrical Properties of Sputtered Tin Oxide Thin Films. (in Korean)", J. Microelectron. Packag. Soc., 25(2), 49 (2018). https://doi.org/10.6117/KMEPS.2018.25.2.049
  14. Y. L. Dong and B. Pan, "A Review of Speckle Pattern Fabrication and Assessment for Digital Image Correlation", Experimental Mechanics, 57(8), 1161 (2017). https://doi.org/10.1007/s11340-017-0283-1
  15. T. I. Lee, M. S. Kim, and T. S. Kim, "Contact-Free Thermal Expansion Measurement of Very Soft Elastomers using Digital Image Correlation", Polymer Testing, 51, 181 (2016). https://doi.org/10.1016/j.polymertesting.2016.03.014
  16. T. C. Chiu and E. Y. Yeh, "Warpage Simulation for the Reconstituted Wafer used in Fan-Out Wafer Level Packaging", Microelectronics Reliability, 80, 14 (2018). https://doi.org/10.1016/j.microrel.2017.11.008
  17. J. H. Lau, M. Li, D. Tian, N. Fan, E. Kuah, W. Kai, M. Li, J. Hao, Y. M. Cheung, Z. Li, K. H. Tan, R. Beica, T. Taylor, C. T. Ko, H. Yang, Y. H. Chen, S. P. Lim, N. C. Lee, J. Ran, C. Xi, K. S. Wee, and Q. Yong, "Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging", IEEE Transactions on Components, Packaging and Manufacturing Technology, 7(10), 1729 (2017). https://doi.org/10.1109/TCPMT.2017.2715185
  18. Y. Okada and Y. Tokumaru, "Precise Determination of Lattice Parameter and Thermal Expansion Coefficient of Silicon Between 300 and 1500 K", Journal of Applied Physics, 56, 314 (1984). https://doi.org/10.1063/1.333965