The Journal of Korea Institute of Information, Electronics, and Communication Technology (한국정보전자통신기술학회논문지)

Korea Information Electronic Communication Technology (한국정보전자통신기술학회)
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Design of Single Power CMOS Beta Ray Sensor Reducing Capacitive Coupling Noise

커패시터 커플링 노이즈를 줄인 단일 전원 CMOS 베타선 센서 회로 설계

  • Jin, HongZhou (Department of Electronic Engineering, Changwon National University) ;
  • Cha, JinSol (Department of Electronic Engineering, Changwon National University) ;
  • Hwang, ChangYoon (Department of Smart Manufacturing Engineering, Changwon National University) ;
  • Lee, DongHyeon (Department of Smart Manufacturing Engineering, Changwon National University) ;
  • Salman, R.M. (Department of Electronic Engineering, Changwon National University) ;
  • Park, Kyunghwan (Electronics and Telecommunications Research Institute) ;
  • Kim, Jongbum (Korea Atomic Energy Research Institute) ;
  • Ha, PanBong (Department of Electronic Engineering, Changwon National University) ;
  • Kim, YoungHee (Department of Electronic Engineering, Changwon National University)
  • Received : 2021.08.10
  • Accepted : 2021.08.21
  • Published : 2021.08.30
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Abstract

In this paper, the beta-ray sensor circuit used in the true random number generator was designed using DB HiTek's 0.18㎛ CMOS process. The CSA circuit proposed a circuit having a function of selecting a PMOS feedback resistor and an NMOS feedback resistor, and a function of selecting a feedback capacitor of 50fF and 100fF. And for the pulse shaper circuit, a CR-RC2 pulse shaper circuit using a non-inverting amplifier was used. Since the OPAMP circuit used in this paper uses single power instead of dual power, we proposed a circuit in which the resistor of the CR circuit and one node of the capacitor of the RC circuit are connected to VCOM instead of GND. And since the output signal of the pulse shaper does not increase monotonically, even if the output signal of the comparator circuit generates multiple consecutive pulses, the monostable multivibrator circuit is used to prevent signal distortion. In addition, the CSA input terminal, VIN, and the beta-ray sensor output terminal are placed on the top and bottom of the silicon chip to reduce capacitive coupling noise between PCB traces.

본 논문에서는 DB하이텍 0.18㎛ CMOS 공정을 이용하여 진성난수 생성기에 사용되는 베타선 센서 회로를 설계하였다. CSA 회로는 PMOS 피드백 저항과 NMOS 피드백 저항을 선택하는 기능, 50fF과 100fF의 피드백 커패시터를 선택하는 기능을 갖는 회로를 제안하였다. 그리고 펄스 셰이퍼(pulse shaper) 회로는 비반전 증폭기를 이용한 CR-RC2 펄스 셰이퍼 회로를 사용하였다. 본 논문에서 사용한 OPAMP 회로는 이중 전원(dual power) 대신 단일 전원(single power) 사용하고 있으므로 CR 회로의 저항과 RC 회로의 커패시터의 한쪽 노드는 GND 대신 VCOM에 연결한 회로를 제안하였다. 그리고 펄스 셰이퍼의 출력신호가 단조 증가가 아닌 경우 비교기 회로의 출력 신호가 다수의 연속된 펄스가 발생하더라도 단조 다중발진기(monostable multivibrator) 회로를 사용하여 신호 왜곡이 안되도록 하였다. 또한 CSA 입력단인 VIN과 베타선 센서 출력단을 실리콘 칩의 상단과 하단에 배치하므로 PCB trace 간의 커패시터 커플링 노이즈(capacitive coupling noise)를 줄이도록 하였다.

Keywords

Acknowledgement

This research was supported by Nuclear Technology Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Science, ICT & Future Planning (No. 2018M2A8A1083094).

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