Analysis of Warpage of Fan-out Wafer Level Package According to Molding Process Thickness

몰드 두께에 의한 팬 아웃 웨이퍼 레벨 패키지의 Warpage 분석

  • Seung Jun Moon (NEPES Co., Ltd.) ;
  • Jae Kyung Kim (Industrial Technology Research Institute, Kongju National University) ;
  • Euy Sik Jeon (Industrial Technology Research Institute, Kongju National University)
  • Received : 2023.11.30
  • Accepted : 2023.12.12
  • Published : 2023.12.31

Abstract

Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

Keywords

References

  1. Cheong-Ha Jung, Won Seo and Gu-Sung Kim, "A Study of Warpage Analysis According to Influence Factors in FOWLP Structure", Journal of the Semiconductor & Display Technology, 17(4), 42-45 (2018).
  2. Mi Kyoung Lee, Jin Wook Jeoung, Jin Young Ock, Sung-Hoon Choa, "Numerical Analysis of Warpage and Reliability of Fan-out Wafer Level Package," J. Microelectron. Packag. Soc., 21(1), 31-39 (2014). https://doi.org/10.6117/kmeps.2014.21.1.031
  3. Yoon-chul Son, "Fan-out wafer-level packaging (FOWLP) technology trends," J. Electrical & Electronic materials, 34(2), 4-11 (2021).
  4. Geumtaek Kim, Daeil Kwon, "Warpage Analysis during Fan-Out Wafer Level Packaging Process using Finite Element Analysis," J. Microelectron. Packag. Soc., 25(1), 41-45 (2018).
  5. Xiaowu Zhang, Boon Long Lau, Yong Han, Haoran Chen, Ming Chinq Jong, Sharon Pei Siang Lim, Simon Siak Boon Lim, "Addressing Warpage Issue and Reliability Challenge of Fan-out Wafer-Level Packaging (FOWLP)" Electronic Components and Technology Conference (ECTC), IEEE 71st, (2021).
  6. Ghanshyam Gadhiya, Birgit Bramer, Sven Rzepka, Thomas Otto, "Assessment of FOWLP process dependent wafer warpage using parametric FE study," European Microelectronics and Packaging Conference & Exhibition (EMPC), 22nd, (2019).
  7. L. Ji, T.C. Chai, G. See, P. Suo, "Modelling and prediction on process dependent wafer warpage for FOWLP technology using finite element analysis and statistical approach" Electronics Packaging Technology Conference (EPTC), IEEE 22nd, (2020).
  8. Jeong-hyeon Baek, Dong-woon Park, Hak-sung Kim, "Measurement of effective cure shrinkage of EMC using dielectric sensor and FBG sensor," J. Microelectron. Packag. Soc., 29(4), 83-87 (2022).