In summary, a fundamentally new paradigm called System-on-Package could potentially become a complementary alternative to System-on-Chip, thus providing a balanced set of system-level functions between the semiconductor IC and single component package beyond the year 2007. The concurrent engineering and optimization of IC and package could overcome the fundamental IC issues presented above.

Flip chip assembly on organic substrates using ACAs have received much attentions due to many advantages such as easier processing, good electrical performance, lower cost, and low temperature processing compatible with organic substrates. ACAs are generally composed of epoxy polymer resin and small amount of conductive fillers (less than 10 wt. %). As a result, ACAs have almost the same CTE values as an epoxy material itself which are higher than conventional underfill materials which contains lots of fillers. Therefore, it is necessary to lower the CTE value of ACAs to obtain more reliable flip chip assembly on organic substrates using ACAs. To modify the ACA composite materials with some amount of conductive fillers, non-conductive fillers were incorporated into ACAs. In this paper, we investigated the effect of fillers on the thermo-mechanical properties of modified ACA composite materials and the reliability of flip chip assembly on organic substrates using modified ACA composite materials. For the characterization of modified ACAs composites with different content of non-conducting fillers, dynamic scanning calorimeter (DSC), and thermo-gravimetric analyzer (TGA), dynamic mechanical analyzer (DMA), and thermo-mechanical analyzer (TMA) were utilized. As the non-conducting filler content increased, CTE values decreased and storage modulus at room temperature increased. In addition, the increase in tile content of filler brought about the increase of Tg$^{DSC}$ and Tg$^{TMA}$. However, the TGA behaviors stayed almost the same. Contact resistance changes were measured during reliability tests such as thermal cycling, high humidity and temperature, and high temperature at dry condition. It was observed that reliability results were significant affected by CTEs of ACA materials especially at the thermal cycling test. Results showed that flip chip assembly using modified ACA composites with lower CTEs and higher modulus by loading non-conducting fillers exhibited better contact resistance behavior than conventional ACAs without non-conducting fillers.ers.

The issue of reflow profiling continues to be a complex topic. The pains often associated with profiling can be reduced greatly if certain guidelines are followed and if there is a strong understanding of the variables that can be encountered during the reflow process. This paper shall discuss the appropriate guidelines and trouble shooting methods for reflow profiling, and in particular shall focus upon the benefits of implementing the linear ramp-to-spike profile. Delta T(T) is defined as the variation of temperature found on an assembly during the reflow process. Too large of a T can result in soldering defects, so to combat T a Ramp-Soak-Spike(RSS) reflow profile often is utilized. However, when using a newer-style reflow oven, the T often is minimized or eliminated, thus, the soak zone of the reflow profile becomes an unnecessary step. Because of this, the implementation of a linear Ramp-To-Spike(RTS) reflow profile should be considered. Benefits such as reduced energy costs, reduced solder defects, increased efficiency, improved wetting, and a simplification of the reflow profile process may be experienced when using the RTS profile. Included in this paper are the suggested process parameters for setting up the RSS and RTS profiles and the chemical and metallurgical reactions that occur at each set point of these profiles. The paper concludes with a discussion and pictures of several profile-related defects. Each of these defects is described, analyzed, and instructions are given for troublshooting these defects.

Dielectric polymer films produced from benzocyclobutene (BCB) formulations (CYCLOTENE＊ family resins) are known to possess many desirable properties for microelectronic applications; for example, low dielectric constant and dissipation factor, low moisture absorption, rapid curing on hot plate without reaction by-products, minimum shrinkage in curing process, and no Cu migration issues. Recently, BCB-based products for thick film applications have been developed, which exhibited excellent dissipation factor and dielectric constant well into the GHz range, 0.002 and 2.50, respectively. Derived from these properties, the applications are developed in: bumping/wafer level packaging, Ga/As chip ILD, optical waveguide, flat panel display, and lately in BCB-coated Cu foil for build-up board. In this paper, we review the relevant properties of BCB, then the application areas in bumping/wafer level packaging and BCB-coated Cu foil for build-up board.

MEMS, Micro Electro-Mechanical Systems, present one of the greatest advanced packaging challenges of the next decade. Historically hybrid technology, generally thick film, provided sensors and actuators while integrated circuit technologies provided the microelectronics for interpretation and control of the sensor input and actuator output. Brought together in MEMS these technical fields create new opportunities for miniaturization and performance. Integrated circuit processing technologies combined with hybrid design systems yield innovative sensors and actuators for a variety of applications from single crystal silicon wafers. MEMS packages, far more simple in principle than today's electronic packages, provide only physical protection to the devices they house. However, they cannot interfere with the function of the devices and often must actually facilitate the performance of the device. For example, a pressure transducer may need to be open to atmospheric pressure on one side of the detector yet protected from contamination and blockage. Similarly, an optical device requires protection from contamination without optical attenuation or distortion being introduced. Despite impediments such as package standardization and complexity, MEMS markets expect to double by 2003 to more than ＄9 billion, largely driven by micro-fluidic applications in the medical arena. Like the semiconductor industry before it. MEMS present many diverse demands on the advanced packaging engineering community. With focused effort, particularly on standards and packaging process efficiency. MEMS may offer the greatest opportunity for technical advancement as well as profitability in advanced packaging in the first decade of the 21st century! This paper explores MEMS packaging opportunities and reviews specific technical challenges to be met.

MCM technology languished troughout most of the 1990's due to high costs resulting from low yields and issues with known god die. During the last five years of the decade new developments in chip scale packages and high density, build up multi-layer printed wiring boards created new opportunities to design and produce ultra miniaturized modules using conventional surface mount manufacturing capabilities. Focus on the miniaturization of substrate based packages such as ball grid arrays (BGAs) resulted in chip scale packages (CSPs) offering many of the benefits of flip chip along with the handling, testing, manufacturing and reliability capabilities of packaged deviced. New developments in the PWB industry sought to reduce the size, weight, thickness and cost of high density interconnect (HDI) substrates. Shrinking geometries of vias and new constructions significantly increased the interconnect density available for MCM-L applications. This paper describes the most promising CSP and HDI technologies for portable products, high performance computing and dense multi-chip modules.

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology fur their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electrodes nickel, solder jetting, stud bumping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

기판과의 동시소성에 의한 고주파 MCM-C(Multi-Chip-Module-Cofired)용 저항을 제작하고 6 GHz 까지의 RF 특성을 측정하였다. 기판은 저온 소성용 기판으로서 총 8층으로 구성하였으며, 7층에 저항체 및 전극을 인쇄하고 Via를 통하여 기판의 최상부까지 연결되도록 하였다 저항체 Pastes, 저항체의 크기, Via의 길이 변화에 따라서 저항의 RF 특성은 고주파일수록 더욱 DC 저항값에서부터 변화되는 양상을 보였다. 내부저항의 등가회로를 구현한 결과, 저항은 전송선로, Capacitance 성분이 혼재되어 있는 것으로 나타났으며 전극의 형태에 따라 Capacitance 성분이 많은 차이를 나타내었다.

Shear strength of BGA solder joints on Cu pad was studied for Cu-contained Sn n.5 a and 2.5wt.% Cu) and Sn-Pb (o.5wt.% Cu) solders, with emphasis on the roles of the C Cu-Sn intermetallic layer thickness and the roughness of the interface between the i intermetallic layer and solder. The shear strength test was performed both for a as-soldered s이der joints with soldering reaction times of 1, 2, 4 min and for aged s이der j joints at 170 C up to 16 days. The Cu addition to both pure Sn and eutectic Sn-Pb s solders increased the intermetallic layer thickness at both soldering and aging t temperatures. The Cu addition also resulted in changes in the roughness of the interface b between the intermetallic layer and solder at as-soldered states. With increasing Cu c content. the interface roughened for Sn-Cu solders whereas it flattened for Sn-Pb-Cu s solders. The shear fractures in all solder joints investigated were confined in the bulk s solder rather than through the intermetallic layer. Therefore, the effect of Cu content in s solders on the shear strength of the solder joints was primarily attributed to its i influence on the micros$\sigma$ucture of bulk solder, such as the size and spatial distributions of CU6Sn5 precipitates. In addition, the critical intermetallic layer thickness for a m maximum shear strength seemed to depend on the Cu content in bulk solder.older.

In an attempt to estimate the wetting properties of wettable metal layers by wetting balance method, an analysis of wetting curves of the coating layer was performed. Based on the analysis, wetting properties of UBM-coated Si-plate were estimated by the new wettability indices. The wetting curves of the one and both sides-coated UBM layers have the similar shape and show the similar tendency to the temperature. So the wetting property estimation of one side coating is possible with wetting balance method. For UBM of Si-chip, Cr/Cu/Au UBM is better than Ti/Ni/Au in the point of wetting time. At general reflow temperature, the wettability of high melting point solders(Sn-Sb, Sn-Ag) is better than that of few melting point ones(Sn-Bi, Sn-In).The contact angle of the one side coated plate to the solder can be calculated from the farce balance equation by measuring the static state force and the tilt angle.

To evaluate the possibility of the partial melting soldering. wettability of partial melted solders was measured using wetting balance. Off eutectic Sn-Pb allows are wettable in their partial melting zone. Especially, Pb rich alloys showed excellent wettability while wettability of Sn rich alloys were adequate or poor. It is found that wettability increases over $200^{\circ}C$ regardless of composition liquid fraction and phases of the original alloy Sn-7Ag alloy showed good wettability in their partial melting zone, while Sn-65Bi alloy was non-wettable under their melting points.

The properties of polyimide for interlayer dielectric applications are investigated during plasma etching of aluminum on it. Chlorine-based plasma generally used for aluminum etching results in an increase in the (dielectric constant of polyimide, while $SF_6$ plasma exhibits a high polyimide etch rate and a reducing effect of the dielectric constant. The leakage current of polyimide is significantly suppressed after plasma exposure. An optimal combination of Al etch with $Cl_6$ plasma and polyimide etch with $SF_6$ plasma is expected to be a good tool for realizing multilevel metallization structures.

We have studied etching characteristic of Ta film using Electron Cyclotron Resonance (ECR) etcher system. Microwave source power. RF bias power. and working pressure were varied to investigate the etch Profile. And we have used two step etching method to acquire the goWe have studied etching characteristic of Ta film using Electron Cyclotron Resonance (ECR) etcher system. Microwave source power. RF bias power. and working pressure were varied to investigate the etch Profile. And we have used two step etching method to acquire the good etch profile preventing the microloading effect.od etch profile preventing the microloading effect.

The texture of Al/Ti thin films deposited on low-dielectric polymer substrates has been investigated. Fifty-nm-thick Ti films and 500-nm-thick Al-1%Si-0.5%Cu (wt%) films were deposited sequentially onto low-k polymers and SiO$_2$ by using a DC magnetron sputtering system. The texture of Al thin film was determined using X-ray diffraction (XRD) theta-2theta ($\theta$-2$\theta$) and rocking curve and the microstructure of Al/Ti films on low-k polymer and SiO$_2$ substrates was characterized by Transmission electron microscopy (TEM). hall thin films deposited on SiO$_2$ had stronger texture than those deposited on low-k polymer. The texture of Al thin films strongly depended on that of Ti films. Cross-sectional TEM resealed that Brains of Ti films on SiO$_2$ substrates had grown perpendicular to the substrate, while the grains of Ti films on SiLK substrates were farmed randomly. The lower degree of 111 texture of Al thin films on low-k polymer was due to Ti underlayer.

Recently, carbon nanotube has been investigating for field emission display ( (FED) applications due to its high electron emission at relatively low electric field. However, the growing of carbon nanotube generally requires relatively high temperature processing such as arc-discharge (5,000 ~ $20,000^{\circ}C$) and laser evaporation (4,000 ~ $5,000^{\circ}C$) methods. In this presentation, low temperature growing of carbon nanotube by plasma enhanced chemical vapor deposition (PECVD) using nickel catalyst which is compatible to conventional FED processing temperature will be described. Carbon n notubes with average length of 100 run and diameter of 2 ~ $3\mu$ill were successfully grown on silicon substrate with native oxide layer at $550^{\circ}C$using nickel catalyst. The morphology and microstructure of carbon nanotube was highly depended on the processing temperature and nickel layer thickness. No significant carbon nanotube growing was observed with samples deposited on silicon substrates without native oxide layer. This is believed due to the formation of nickel-silicide and this deteriorated the catalytic role of nickel. The formation of nickel-silicide was confirmed by x-ray analysis. The role of native oxide layer and processing parameter dependence on microstructure of low temperature grown carbon nanotube, characterized by SEM, TEM XRD and R없nan spectroscopy, will be presented.

Cantilever-shaped lateral field emitters were fabricated and their electrical characteristics were tested. As shown in Fig.1, poly-silicon cantilevers were fabricated by the surface micromachining and they were used to the vacuum magnetic field sensors. The tunneling devices were vacuum sealed with the tubeless packaging method, as shown in Fig.2 and Fig.3. The soda-lime glasses were used for better encapsulation, so the sputtered silicon and the glass layers on the soda-lime glasses were bonded together at 1x10$^{-6}$ Torr. The getter was activated after the vacuum sealing fur the stable emissions. The devices were tested outside of the vacuum chamber. Through vacuum packaging, the tunneling sensors can be utilized. Fig.4 shows that the sensor operates with the switching of the magnetic field. When the magnetic field was applied to the device, the anode currents were varied by the Lorentz force. The difference of anode currents can be varied with the strength of the applied magnetic field.

In order to form a uniform oxidation layer and spinel crystalline phase that has been help strong bonding in Kovar(Fe-29Ni-17Co)-to-glass sealing, the humidified nitrogen and nirtogen/hydrogen mixture was used as an oxidation atmosphere. Kovar oxidation was diffusion-controlled reaction and the activation energy was 25~32 kcal/mol at $600~900^{\circ}C.$ After oxidation at $600^{\circ}C, $ the oxidation layer was under 1 $\mu\textrm{m}$ thickness and crystalline phase was spinel which was found to be suitable for the Kovar-to-glass sealing. The Kovar-to-glass seal was carried out at $1010^{\circ}C$ and humidified nitrogen/hydrogen mixture atmosphere. Sealing properties were tested by Leak tester and SEM.

Nd:YAG laser of 355nm wavelength, which amounts to 3.5eV, produced by a harmonic generator was used to create Ag metallic particles as seeds for nucleation in photosensitive glass containing Ag+ and Ce3+. The pulse widths and frequency of the laser were 8ns and 10Hz, respectively. For crystalline growth, heat-treatment following laser irradiation was carried out at $570^{\circ}C$ fur 1h. Then, the LiAlSi3O8. crystal phase appeared in the laser irradiated lithium aluminum silicate glass. We present the effect of laser-induced nucleation compared with spontaneous nucleation by heat treatment for crystallization in the glass.

New single-source precursor, [AlCI3:NH2tBu] was synthesized for AlN thin f film processing with AICI3 (Aluminum Chloride) and tBuNH2 (tert-butylamine). AlN thin films for packaging aspplication were deposited on sapphire substrate by a atmosph하ie-pressure MOCVD. In most of other study methyl-based AI precursors w were used for source, But herein Aluminum Chloride was used for as AI source i in order to prevent the carbon contamination in the films and stabilize the p precursor. New precursor showed the very high gas vapor pressure so it allowed to m make the film under atmospheric-pressure and get the high purified film. High q quality AlN thin film was obtained at 700 to $900^{\circ}C$. The new precursor was p purified by a sublimation technique and help to fabricate high purity film. It s showed high vapor pressure, which is able to a critieal factor for the high purity a and atmospheric CVD of AlN. High Quality AIN thin film was obtained at $700-900^{\circ}C$. The AIN film was characterized by RBS

A new type of low voltage driven SrTiO3 varistor was investigated. $SrTi3_3$ sintered with CuO-SiO2 additions, the sintering temperature was reduced to 1250-1300C. With the sintering additives, the semiconducting SrTi03 was able to fabricate single time sintering in reducing atmosphere(95% N2 + 5% H2), The non-linear coefficient value was 10.3 and the operating voltage was about 7 V.