• Korean Journal of Materials Research
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• v.17 no.12
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• pp.676-681
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• 2007

According to progress rapidly digitalization, networked and mobilization of electronics industry, there are demands for being smaller, thinner, more light, and more efficient complex functions of electronic devices which are wireless devices, semi-conductors, packages and mobile devices. Therefore, the solder resist on a printed circuit board have been required with the high resolution and the eco-friendly materials in the surface treatments such as high heating process and coating process with electrolysis. In this study, the photoinitiator initiator and monomers of the solder resist were prepared with their contents for reducing the occurrence of the under-cut. We investigated the sample surface by UV/VIS spectrometer, FT-IR, OM after HASL and ENIG process. From our results, it is possible to get a high adhesion of resist with optimal contents between the photoinitiator initiator and monomers after surface treatments.

• Applied Chemistry for Engineering
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• v.20 no.2
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• pp.172-176
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• 2009

In this research, we defined the basic structure of soft etching material as $H_2SO_4/H_2O_2$, and used additives as inhibitor, surfactant, and stabilizer. By analyzing influence to surface roughness and change of etching rate related to type and density of additives, we research to develop soft etching material having the same adhesiveness as existing etching material. As a result of research, it is estimated that after densities of $H_2O_2$ and $H_2SO_4$ are 3%, 4% respectively, 500 ppm of amine type 5-Azol, as inhibitor, and 600 ppm of PEI, as surfactant, and 10 ppm of phosphoric acid, as stabilizer, are added, is the most reasonable surface roughness and etching rate. As result of solder test, it is estimated that solder resist ink did not peel away or curl up and have reliable adhesiveness.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.73-82
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• 2003

Recently, PWB(Printed Wiring Board) has been recognized in the field of microelectronic package as core technology for designing or manufacturing. PWB is the structure stacked by several materials with different thermophysical properties, which shows the different CTEs(Coefficient or Thermal Expansions) during the fabrication process and causes a lot of defects such as warpage, shrinkage, dimension, etc. Thermal deformation of PWB is affected mainly by the volume change of solder-resist among fabrication parameters. Therefore, thermal deformation of PBGA and CSP consisting of 2 layers and 4 layers was studied with solder-resist process. When over 30% in volume fraction of solder-resist, thermal deformation of 2-layered PWB was min. 40% higher than that of 4-layered PWB because 4-layered PWB contained the layer with high toughness such as prepreg, which counterbalanced the thermal deformation of solder-resist. Otherwise, when below 30%, PWB showed similar thermal deformation without regard to layers and design.

• Journal of Welding and Joining
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• v.17 no.2
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• pp.61-65
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• 1999

Because of the need for packages which accommodate high pin count, high density and high speed device, PBGA(plastic ball grid array) package gets more spotlight. But the substrate material which is used for PBGA package is in nature susceptible to moisture penetration. The objective of the study is to find out the path of delamination in the stacked structure of substrate. To increase the adhesion between the cooper laminate and PSR(photo solder resist) which is the weakest part, experiments were performed by changing parameters of printing pre-treatment and post-treatment process. As a result of experiments, the factor effects on the adhesion between the cooper laminate and PSR is caused by all of the pre-treatment and post-treatment condition. A considerable change was observed depending on the amount of UV irradiation after thermal cure which is typical of printing post-treatment condition rather than pre-treatment condition.

• ETRI Journal
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• v.35 no.4
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• pp.625-631
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• 2013

For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.2 s.39
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• pp.1-7
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• 2006

In this paper, warpage magnitude and shape of printed-circuit board in case that properties of core and thickness of solder resist are varied are investigated. The cause of warpage is coefficient of thermal expansion differences of stacked materials. Therefore, we need small difference of coefficient of thermal expansion that laminated material, and need to decrease asymmetric of top side and bottom side in structure shape. Also, we can control occurrence of warpage heightening hardness of core in laminated material. Composite material that make core are exploited in connection with the structural bending twisting coupling resulting from directional properties of fiber reinforced composite materials and from ply stacking sequence. If we use such characteristic, we can control warpage with change of material properties. In this paper, warpage of two layer stacked chip scale package is investigated, and evaluate improvement result using an experiment and finite element method tool.

• Applied Chemistry for Engineering
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• v.20 no.6
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• pp.622-627
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• 2009

Using an alkali-solution developable photosensitive resin and a carbon black as a conductive filler, photo-patternable pastes for polymer thick film resistor were fabricated and evaluated. A photo solder resist (PSR), which is usually used as protecting layer of printed circuit board (PCB), was used as a photosensitive resin so that ultraviolet exposure and alkali-aqueous solution development of paste were possible. After fabricating the photosensitive polymer resistor paste, the electrical properties of thick film resistors were measured using PCB test boards. Sheet resistance was decreased with increasing amount of carbon black, but the developability was limited in excess loading of carbon black. The sheet resistance was also reduced by re-curing and the change rate was smaller in higher carbon black loading. Moreover, finely patterned meander-type thick film resistors were fabricated using photo-process and large resistance up to several tens of sheet resistance could be obtained in small area by this technique.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.4
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• pp.31-39
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• 2021

In this paper, warpage analysis that separates PCB for PoP (Package on Package) into unit and substrate using FEM (Finite Element Method), analysis of the effect of layer thickness on warpage, and SN (Signal-to-Noise) ratio by Taguchi method was carried. According to the analysis result, the contribution of the circuit layer on warpage was very high in the unit PCB, and the contribution of the outer layer was particularly high. On the other hand, the substrate PCB had a high influence of the circuit layer on warpage, but it was relatively low compared to the unit PCB, and the influence of the solder resist was rather increased. Therefore, considering the unit PCB and the substrate PCB at the same time, it is desirable to design the PCB for PoP layer-by-layer structure so that the outer and inner circuit layers are thick, the top solder resist is thin, and the thickness of the bottom solder resist is between 5 ㎛ and 25 ㎛.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.1
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• pp.75-81
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• 2015

In this paper, numerical analysis by finite element method and parameter design by the Taguchi method were used to reduce warpage of a two passive components embedded double side substrate for PoP(Package on Package). The effect of thickness of circuit layers (L1, L2) and thickness of solder resist (SR_top, SR_BTM) were analyzed with 4 variations and 3 levels(minimum, average and maximum thickness) to find optimized thickness conditions. Also, paste effect of solder resist on unit area of top surface was analyzed. Finally, experiments was carried out to prove numerical analysis and the Taguchi method. Based on the numerical and experimental results, it was known that circuit layer in ball side of substrate was the most severe determining deviation for reducing warpage. Buried circuit layer in chip side, solder resist and were insignificant effects on warpage relatively. However, warpage decreased as circuit layer in ball side thickness increased but effect of solder resist and circuit layer in chip side thickness were conversely.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.60-67
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• 2014

The ability of electronic packages and assemblies to resist solder joint failure is becoming a growing concern. This paper reports on a study of high speed shear energy of Sn-4.0wt%Ag-0.5wt%Cu (SAC405) solder with different electroless Ni-P thickness, with $HNO_3$ vapor's status, and with various pre-conditions. A high speed shear testing of solder joints was conducted to find a relationship between the thickness of Ni-P deposit and the brittle fracture in electroless Ni-P deposit/SAC405 solder interconnection. A focused ion beam (FIB) was used to polish the cross sections to reveal details of the microstructure of the fractured pad surface with and without $HNO_3$ vapor treatment. A scanning electron microscopy (SEM) and an energy dispersive x-ray analysis (EDS) confirmed that there were three intermetallic compound (IMC) layers at the SAC405 solder joint interface: $(Ni,Cu)_3Sn_4$ layer, $(Ni,Cu)_2SnP$ layer, and $(Ni,Sn)_3P$ layer. The high speed shear energy of SAC405 solder joint with $3{\mu}m$ Ni-P deposit was found to be lower in pre-condition level#2, compared to that of $6{\mu}m$ Ni-P deposit. Results of focused ion beam and energy dispersive x-ray analysis of the fractured pad surfaces support the suggestion that the brittle fracture of $3{\mu}m$ Ni-P deposit is the result of Ni corrosion in the pre-condition level#2 and the $HNO_3$ vapor treatment.