대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)

대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

$2{\mu}m$ CMOS P-WELL DOUBLE METAL TECHNOLOGY

  • 신철호 (삼성반도체통신(주) 연구소) ;
  • 안경호 (삼성반도체통신(주) 연구소) ;
  • 정은승 (삼성반도체통신(주) 연구소) ;
  • 진주현 (삼성반도체통신(주) 연구소)
  • Shin, C.H. (R & D CENTER, SAMSUNG Semiconductor & Telecommunication Co. Ltd.) ;
  • Ahn, K.H. (R & D CENTER, SAMSUNG Semiconductor & Telecommunication Co. Ltd.) ;
  • Jung, E.S. (R & D CENTER, SAMSUNG Semiconductor & Telecommunication Co. Ltd.) ;
  • Jin, J.H. (R & D CENTER, SAMSUNG Semiconductor & Telecommunication Co. Ltd.)
  • 발행 : 1987.07.03
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초록

A $2{\mu}m$ CMOS P-well double metal technology has been developed. Phosphorus deep implantation and drive-in diffusion steps were utilized to prevent the low voltage bulk punch through in the short channel, 1.6[${\mu}m$] Leff, PMOS device. Double metal process with the rules of 5[${\mu}m$] 1st metal pitch and 7[${\mu}m$] 2nd metal pitch was successfully implemented by using VLTO, low temperature oxide, as on intermetal dielectric.

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