대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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Circuit Design of a Ternary Flip-Flop Using Ternary Logic Gates

  • Kim, Jong-Heon (Circuit & System Lab. Dept. of Electronic Eng. Inha University. KOREA) ;
  • Hwang, Jong-Hak (Circuit & System Lab. Dept. of Electronic Eng. Inha University. KOREA) ;
  • Park, Seung-Young (Circuit & System Lab. Dept. of Electronic Eng. Inha University. KOREA) ;
  • Kim, Heung-Soo (Circuit & System Lab. Dept. of Electronic Eng. Inha University. KOREA)
  • 발행 : 2000.07.01
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초록

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

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