대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Generation of Control Signals in High-Level Synthesis from SDL Specification

  • Kwak, Sang-Hoon (Department of Information and Communication, Kwang-Ju Institute of Science and Technology) ;
  • Kim, Eui-Seok (Department of Information and Communication, Kwang-Ju Institute of Science and Technology) ;
  • Lee, Dong-IK (Department of Information and Communication, Kwang-Ju Institute of Science and Technology) ;
  • Baek, Young-Seok (IC Design Department, Electronics and Telecommunications Research Institute) ;
  • Park, In-Hak (IC Design Department, Electronics and Telecommunications Research Institute)
  • 발행 : 2000.07.01
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초록

This paper suggests a methodology in which control signals for high-level synthesis are generated from SDL specification. SDL is based on EFSM(Extended Finite State Machine) model. Data path and control part are partitioned into representing data operations in the from of scheduled data flow graph and process behavior of an SDL code in forms of an abstract FSM. Resource allocation is performed based on the suggested architecture model and local control signals to drive allocated functional blocks are incorporated into an abstract FSM extracted from an SDL process specification. Data path and global controller acquired through suggested methodology are combined into structural VHDL representation and correctness of behavior for final circuit is verified through waveform simulation.

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