한국정보디스플레이학회:학술대회논문집
- 2007.08a
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- Pages.806-809
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- 2007
High Speed Parallel Fault Detection Design for SRAM on Display Panel
- Jeong, Kyu-Ho (School of Electronic and Electrical Eng., Hongik Univ.) ;
- You, Jae-Hee (School of Electronic and Electrical Eng., Hongik Univ.)
- Published : 2007.08.27
Abstract
SRAM cell array and peripheral circuits on display panel are designed using LTPS process. To overcome low yield of SOP, high speed parallel fault detection circuitry for memory cells is designed at local I/O lines with minimal overhead for efficient memory cell redundancy replacement. Normal read/write and parallel test read/write are simulated and verified.