Journal of the Korean Institute of Telematics and Electronics (대한전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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IC Worst Case Analysis Considered Random Fluctuations on Fabrication Process

제조 공정상 랜덤 특성을 고려한 IC 최악조건 해석

  • 박상봉 (고려대학교 전자계산기공학과) ;
  • 박노경 (고려대학교 전자계산기공학과) ;
  • 전흥우 (고려대학교 전자계산기공학과) ;
  • 문대철 (고려대학교 전자계산기공학과) ;
  • 차균현 (고려대학교 전자계산기공학과)
  • Published : 1988.06.01
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Abstract

The CMOS physical parameters are extracted using by processing models in fabrication steps, processing parameters, fabrication disturbances, control parameters. Statistical CMOS process and device simulator is proposed to evaluate the effect of inherent fluctuations in IC fabrication. Using this simulator, we perform worst case analysis in terms of statistically independent disturbances and compare this proposed method to Monte Carlo method, previous Worst Case method. And simulation results with this proposed method are more accurate than the past worst case analysis. This package is written in C language and runs on a IBM PC AT(OPUS).

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