Journal of the Korean Ceramic Society (한국세라믹학회지)

The Korean Ceramic Society (한국세라믹학회)
권호 표지
DOI QR코드

DOI QR Code

Effect of Firing Temperature on Microstructure and the Electrical Properties of a ZnO-based Multilayered Chip Type Varistor(MLV)

소성온도에 따른 ZnO계 적층형 칩 바리스터의 미세구조와 전기적 특성의 변화

  • Kim, Chul-Hong (Department of Inorganic Materials Engineering, Kyungpook National University) ;
  • Kim, Jin-Ho (Department of Inorganic Materials Engineering, Kyungpook National University)
  • 김철홍 (경북대학교 무기재료공학과) ;
  • 김진호 (경북대학교 무기재료공학과)
  • Published : 2002.01.01
Download PDF
⟨ Previous Next ⟩

Abstract

Microstructure and the electrical porperties of a ZnO-based multilayered chip-type varistor(abbreviated as MLV) with Ag/Pd(7:3) inner electrode have been studied as a function of firing of temperature. At 1100$^{\circ}$C, inner electrode layers began to show nonuniform thickness and small voids, which resulted in significant disappearance of the electrode pattern and delamination at 1100$^{\circ}$C. MLVs fired at 950$^{\circ}$C showed large degradation in leakage current, probably due to incomplete redistribution of liquid and transition metal elements in pyrochlore phase decomposition. Those fired at 1100$^{\circ}$C and above, on the other hand, revealed poor varistor characteristics and their reproductibility, which are though to stem from the deformation of inner electrode pattern, the reaction between electrode materials and ZnO-based ceramics, and the volatilization of $Bi_2O_3$. Throughout the firing temperature range of 950∼1100$^{\circ}$C, capacitance and leakage current increased while breakdown voltage and peak current decreased with the increase of firing temperature, but nonlinear coefficient and clamping ratio kept almost constant at ∼30 and 1.4, respectively. In particular, those fired between 1000$^{\circ}$C and 1050$^{\circ}$C showed stable varistor characteristics with high reproducibility. It seems that Ag/Pd(7:3) alloy is one of the electrode materials applicable to most ZnO-based MLVs incorporating with $Bi_2O_3$ when cofired up to 1050$^{\circ}$C.

소성온도에 따른 ZnO계 적층형 세라믹 칩 바리스터(약칭 MLV)의 미세구조와 전기적 특성의 변화를 조사하였다. 소성온도 1100$^{\circ}$C에서 Ag/Pd(7:3) 내부전극층의 두께가 불균일하게 변화하면서 부분적인 공극이 발생하기 시작하고, 1150$^{\circ}$C에서는 상당한 전극 패턴의 소멸과 박리가 관찰되었다. 950$^{\circ}$C로 소성한 MLV의 경우 누설전류의 열화가 특히 컸는데 이는 미반응의 pyrochlore상이 잔류하여 액상과 천이원소의 균일한 분포가 일어나지 않았기 때문이라 사료된다. 1100$^{\circ}$C 이상의 온도로 소성한 경우에는 바리스터 특성 및 그 재현성의 저하가 관찰되었는데, 이는 내부전극의 소멸, 전극물질과 소체의 반응, 그리고 $Bi_2O_3$의 휘발에 기인한 것으로 보인다. 한편, 950∼1100$^{\circ}$C의 전 소성온도 범위에 걸쳐 온도가 증가할수록 정전용량과 누설전류는 증가하고 항복전압과 피크전류는 감소하였으나, 비선형계수와 클램핑 비는 각각 ∼30 및 1.4로 거의 일정한 값을 유지하였다. 특히 1000∼1050$^{\circ}$C 소성체의 경우 칩 바리스터에 적합한 바리스터 특성이 재현성 있게 나타났다. 결과적으로 Ag/Pd(7:3) 합금은 1050$^{\circ}$C의 동시 소성 온도이하에서는 $Bi_2O_3$를 함유한 대부분의 ZnO계 MLV의 내부전극으로 충분히 사용가능한 것으로 판단된다.

Keywords

References

  1. L. H. Harris, 'Component Handling with ESD Control,' pp. 749-781 in Passive Electronic Component Handbook, 2nd ed., Ed. by Charles. A. Harper, McGraw-HiH, U. S., 1997
  2. D. R. Clarke. 'Varistor Ceramics,' J. Am. Ceram. Soc.. 82 "3" 485-502 (1999) https://doi.org/10.1111/j.1151-2916.1999.tb01793.x
  3. T. K. Gupta, 'Application of Zinc Oxide Varistors,' J. Am. Ceram. Soc., 73 "7" 1817-40 (1990) https://doi.org/10.1111/j.1151-2916.1990.tb05232.x
  4. L. M. Levinson and H. R. PhilipP, 'Zinc Oxide Varistors -A Review,' Am. Ceram. Soc. Bull., 65 "4" 639-46 (1986)
  5. K. Eda, 'Zinc Oxide Varistors,' IEEE Trans. Etect. Ins., 5 "6" 28-41 (1989)
  6. M. Matsuoka, 'Non-ohmic Properties of Zinc Oxide Ceram-ics,' Jpn. J. Appt. Phys., 10 736-46 (1971) https://doi.org/10.1143/JJAP.10.736
  7. N. Shohara et al., 'Multilayered Ceramic Chip Varistor,' pp. 329-337 in Ceramic Transaction Vol. 3, Advances in Varis-tor Technology, Ed. by L. M. Levinson, The American Ceramic Society, U. S., 1989
  8. Murata Manufacturing Co., Ltd., 'Monolithic Type Varis-tor,' U. S. Pat. No. 5 119 062, 1992
  9. Industrial Technology Research Institute, 'Multilayer ZnO Vaiistor,' U. S. Pat. No. 5 369 390, 1994
  10. TDK Corporation, 'Laminated Chip Vanstor and Produc-tion Method Thereof,' U. S. Pat. No. 5 994 995, 1999
  11. Murata Manufacturing Co., Ltd., 'Monolithic Varistor,' U. S. Pat. No. 6 184 770 B1, 2001
  12. C. H. Kim and J. H. Kim, 'Sintehng and the Electrical Properties of Co-doped ZnO-$Bi_2O_3-Sb_2O_3$ Varistor System,' J. Kor. Ceram. Soc., 37 "2" 186-93 (2000)
  13. F. J. Toal, J. P. Dougherty and C. A. Randall, 'Processing and Electrical Characterization of a Varistor-capacitor Cofi-red Multilayer Device,' J. Am. Ceram. Soc., 81 "9" 2371-80 (1998) https://doi.org/10.1111/j.1151-2916.1998.tb02633.x
  14. J. Kim, T. Kimura and T. Yamaguchi, 'Sintering of Zinc Oxide Doped with Antimony Oxide and Bismuth Oxide,' J. Am. Ceram. Soc.. 72 "8" 1390-95 (1989) https://doi.org/10.1111/j.1151-2916.1989.tb07659.x
  15. H. Kanai and M. Imai, 'Effects of SiO$_2 and Cr_2O_3$ on the Formation Process of ZnO Varistors,' J. Mat. Sci., 23 4379-82 (1988) https://doi.org/10.1007/BF00551935
  16. M. Inada, 'Formation Mechanism of Nonohmic Zinc Oxide Ceramics,' Jpn. J. Appt. Phys., 19 "3" 1361-68 (1977)
  17. C. H. Kim and J. H. Kim, 'Sintering Behavior and Elec-trical Properties of Cr-doped ZnO-$Bi_2O_3-Sb_2O_3$ Varistor System,' The Korean Ceramic Society Fall Meeting, Oct. 22-23, 1999
  18. S. F. Wang and J. P. Dougherty, 'Silver-palladium Thick-film Conductors,' J. Am. Ceram. Soc., 11 "12" 3051-72 (1994)
  19. T. K. Gupta, 'Microstructural Engineeiing through Donor and Acceptor Doping in the Grain and Grain Boundary of a Polycrystalline Semiconducting Ceramic,' J. Mat. Res., 7 "12" 3280-95 (1992) https://doi.org/10.1557/JMR.1992.3280
  20. C. H. Kim and J. H. Kim, 'Voltage Transient Response of a ZnO-based Multilayered Chip Varistor Doped with Alum(AlK(SO$_4$)2. 12H$_2$O),' Key Engineering Materiats (tobe published)