Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Trap Generation during SILC and Soft Breakdown Phenomena in n-MOSFET having Thin Gate Oxide Film

박막 게이트 산화막을 갖는 n-MOSFET에서 SILC 및 Soft Breakdown 열화동안 나타나는 결함 생성

  • 이재성 (위덕대학교 정보통신공학부)
  • Published : 2004.08.01
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Abstract

Experimental results are presented for gate oxide degradation, such as SILC and soft breakdown, and its effect on device parameters under negative and positive bias stress conditions using n-MOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both interface and oxide bulk traps are found to dominate the reliability of gate oxide. However, for positive gate voltage, the degradation becomes dominated mainly by interface trap. It was also found the trap generation in the gate oxide film is related to the breakage of Si-H bonds through the deuterium anneal and additional hydrogen anneal experiments. Statistical parameter variations as well as the “OFF” leakage current depend on both electron- and hole-trapping. Our results therefore show that Si or O bond breakage by tunneling electron and hole can be another origin of the investigated gate oxide degradation. This plausible physical explanation is based on both Anode-Hole Injection and Hydrogen-Released model.

두께가 3nm인 게이트 산화막을 사용한 n-MOSFET에 정전압 스트레스를 가하였을 때 관찰되는 SILC 및 soft breakdown 열화 및 이러한 열화가 소자 특성에 미치는 영향에 대해 실험하였다. 열화 현상은 인가되는 게이트 전압의 극성에 따라 그 특성이 다르게 나타났다. 게이트 전압이 (-)일 때 열화는 계면 및 산화막내 전하 결함에 의해 발생되었지만, 게이트 전압이 (＋)일 때는 열화는 주로 계면 결함에 의해 발생되었다. 또한 이러한 결함의 생성은 Si-H 결합의 파괴에 의해 발생할 수 있다는 것을 중수소 열처리 및 추가 수소 열처리 실험으로부터 발견하였다. OFF 전류 및 여러 가지 MOSFET의 전기적 특성의 변화는 관찰된 결함 전하(charge-trapping)의 생성과 직접적인 관련이 있다. 그러므로 실험 결과들로부터 게이트 산화막으로 터널링되는 전자나 정공에 의한 Si 및 O의 결합 파괴가 게이트 산화막 열화의 원인이 된다고 판단된다. 이러한 물리적 해석은 기존의 Anode-Hole Injection 모델과 Hydrogen-Released 모델의 내용을 모두 포함하게 된다.

Keywords

References

  1. D. J. DiMaria and E. Cartier, 'Mechanism for Strss-induced leakage currents in thin silicon dioxide films,' J. Appl. Phys, Vol. 78, No. 6, pp. 3883-3894, 1995 https://doi.org/10.1063/1.359905
  2. K. F. Schuegraf and C. Hu, 'Hole injection SiO2 breakdown model for very low voltage lifetime extrapolation,' IEEE Trans. Electron Devices, Vol. 41, No. 5, pp. 761-766, 1994 https://doi.org/10.1109/16.285029
  3. E. Rosenbaum and L. F. Register, 'Mechanism of stress-induced leakage current in MOS capacitors,' IEEE Trans. Electron Devices, Vol. 44, pp. 317-323, 1997 https://doi.org/10.1109/16.557724
  4. M. Houssa, T. Nigam, P. W. Mertens and M. M. Heyns, 'Model for the current-voltage characteristics of ultrathin gate oxides after soft breakdown,' J. Appl. Phys, Vol. 84, No. 8, pp. 4351-4355 https://doi.org/10.1063/1.368654
  5. E. M. Vogel, D. W. Heh, J. B. Bernstein and J. S. Suehle, 'Impact of the trapping of anode hot holes on silicon dioxide breakdown,' IEEE Electron Device Lett., Vol. 23, pp. 667-669, 2002 https://doi.org/10.1109/LED.2002.805004
  6. E. Rosenbaum and J. Wu, 'Trap generation and breakdown processes in very thin gate oxides,' Microelectronics Reliability, vol. 41, pp. 625-632, 2001 https://doi.org/10.1016/S0026-2714(01)00026-9
  7. H. Guan, M. F. Li, Y. He, B. J. Cho and Z. Dong, 'A thorough study of quasi-breakdown phenomenon of thin gate oxide in dual-gate CMOSFET's,' IEEE Trans. Electron Devices, vol. 47, pp. 1608-1616 https://doi.org/10.1109/16.853038
  8. S. I. Takagi and M. Takayanagi,' Carrier transport properties of thin gate oxide after soft and hard breakdown,' Microelectronic Engineering, vol. 59, pp. 5-15, 2001 https://doi.org/10.1016/S0167-9317(01)00624-4
  9. E. Wu, E. Nowak, J. Aitken, W. Abadeer, L. K. Han and S. Lo, 'Structural dependence of dielectric breakdown in ultra-thin gate oxides and its relationship to soft breakdown modes and device failure,' IEDM Tech. Dig., pp. 187-190, 1998 https://doi.org/10.1109/IEDM.1998.746316
  10. T. Sakura, H. Utsunomiya, Y. Kamakua and K. Taniguchi, 'A detailed study of soft and pre-soft-breakdowns in small geometry MOS structures,' IEDM Tech. Dig., pp. 183-186, 1998
  11. P.J. McWhorter and P.S. Winokur, 'Simple technique for separating the effects of interface traps and trapped-oxide charge in metal-oxide-semiconductor transistors,' Appl. Phys. Lett., vol. 48, pp. 133-135, 1986 https://doi.org/10.1063/1.96974
  12. K. Hess, A. Haggag, W. McMahon, B. Fischer, K. Cheng, J. Lee and J. Lyding, 'Simulation of Si-$SiO_2$ defect generation in CMOS chips: From atomistic structure to chip failure rates,' IEMD Tech. Dig., pp. 93-96, 2000
  13. J. H. Stathis, 'Percolation models for gate oxide breakdown,' J. Appl. Phys., vol. 86, pp. 5757-5766, 1999 https://doi.org/10.1063/1.371590
  14. J. W. Lyding, K. Hess, and I. C. Kizilyalli, 'Reduction of hot electron degradation in metal oxide semiconductor transistors by deuterium processing,' Appl. Phys. Lett., vol. 68, pp. 2526-2528, 1996 https://doi.org/10.1063/1.116172
  15. T. Pompl, H. Wurzer, M. Kerber, R. C. W. Wilkins, and I. Eisele, 'Influence of soft breakdown on NMOSFET device characteristics,' in Proc. IRPS, pp. 82-87, 1999 https://doi.org/10.1109/RELPHY.1999.761596
  16. P. M. Lenahan and J. F. Conley Jr., 'What can electron paramagnetic resonance tell us about the Si-$SiO_2$ system?,' J. Vacuum Science and Technology B, vol. 16, pp. 2134-2154, 1998 https://doi.org/10.1116/1.590301
  17. H. Uchida and T. Ajioka, 'Electron trap center generation due to hole trapping in $SiO_2$ under Fowler-Nordheim tunneling stress,' Appl. Phys. Lett., vol. 51, pp. 433-435, 1987 https://doi.org/10.1063/1.98413