KIEE International Transactions on Electrophysics and Applications

대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

Effect of Soft Error Rate on SRAM with Metal Plate Capacitance

  • Kim Do-Woo (Dept. of Digital Design, Ansung Women's Polytechnic College) ;
  • Gong Myeong-Kook (R & D Center, Optoway, Inc.) ;
  • Wang Jin-Suk (Dept. of Electrical and Electronic Engineering, Chungnam National University)
  • 발행 : 2005.12.01
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초록

We compared and analyzed ASER (Accelerated Soft Error Rate) for cell structures and metal plate capacitance in the fabricated 16M SRAM. Application of the BNW (Buried NWELL) lowered the ASER value compared to the normal well structure. By applying the metal plate capacitor with the BNW, the lowest ASER value can be obtained. The thinner oxide thickness of the metal plate capacitor provides higher capacitance and lower ASER value. The ASER is improved from 2200 FIT to 1000 FIT after sole application of the BNW. However, it is dramatically improved to 15 FIT once the metal plate capacitor is additionally applied.

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참고문헌

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