Gate Length Optimization for Minimum Forward Voltage Drop of IGBTs

  • Moon Jin-Woo (Product Technology Team, Fairchild Semiconductor) ;
  • Park Dong-Wook (LED R&D Lab., R&D Dept., PKG Division, Optical Device, LG Innotek Co. Ltd.) ;
  • Choi Yearn-Ik (School of Electrical and Computer Engineering, College of Information Technology, Ajou University) ;
  • Chung Sang-Koo (Division of Computer, Electronic and Communication Engineering, Yanbian University of Science and Technology)
  • 발행 : 2005.12.01

초록

The forward voltage drop of IGBT is studied numerically and analytically as a function of gate length. An analytical expression is presented for the first time for the surface potential variation along the channel layer under the gate of IGBT. The surface potential drop and the carrier density near the surface allow calculation of the forward voltage drop of IGBT analytically as a function of the gate length. The voltage-drop in the drift region near the gate decreases exponentially, whereas that on the surface increases linearly with increasing the gate length, the sum of which exhibits an optimum gate length, resulting in a minimum forward voltage drop. Based on the surface potential drop, a remodelling of the forward voltage drop of IGBT is also proposed.

키워드

참고문헌

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