Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Multiple-Valued Logic Multiplier for System-On-Panel

System-On-Panel을 위한 다치 논리 곱셈기 설계

  • Published : 2007.02.25
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Abstract

We developed a $7{\times}7$ parallel multiplier using LTPS-TFT. The proposed multiplier has multi-valued logic 7-3 Compressor with folding, 3-2 Compressor, and final carry propagation adder. Architecture minimized the carry propagation. And power consumption reduced by switching the current source to the circuit which is operated in current mode. The proposed multiplier improved PDP by 23%, EDP by 59%, and propagation delay time by 47% compared with Wallace Tree multiplier.

본 논문에서는 저온 다결정 실리콘 공정에서 얻어지는 박막트랜지스터를 이용하여 $7{\times}7$ 병렬처리 곱셈기를 설계하였다. 7개의 부분곱은 Folding 회로를 기본으로 설계된 다치 논리 회로(7-3 Compressor)와 3-2 Compressor를 통해 2비트로 출력되어 Carry Propagating Adder로 전달되는 구조를 통해 Carry전달 지연을 최소화하여 연산속도를 향상시켰다. 그리고 전류모드로 동작하는 곱셈기에서 사용되는 전류원을 부분적으로 차단함으로써 전력소모를 감소시켰다. HSPICE 시뮬레이션 과정을 통해 제안된 곱셈기는 Wallace Tree 곱셈기에 비해 PDP(Power Delay Product)가 23%, EDP(Energy Delay Product)가 59%, 연산 속도가 47% 향상됨을 확인하였다.

Keywords

References

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