Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Low Leakage Input Vector Searching Techniques for Logic Circuits at Standby States

대기상태인 논리 회로에서의 누설전류 최소화 입력 탐색 방법

  • Lee, Sung-Chul (Dept. of Electronics Engineering, Hanyang University) ;
  • Shin, Hyun-Chul (School of Electrical and Computer Engineering, Hanyang University)
  • 이성철 (한양대학교 전자전기제어계측공학과) ;
  • 신현철 (한양대학교 전자컴퓨터공학부)
  • Received : 2009.03.03
  • Published : 2009.10.25
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Abstract

Due to increased integration density and reduced threshold voltages, leakage current reduction becomes important in the semiconductor IC design for low power consumption. In a combinational logic circuit, the leakage current in the standby state depends on the values of the input. In this research, we developed a new input vector control method to minimize the leakage power. A new efficient algorithm is developed to find the minimal leakage vector. It can reduce the leakage current by 15.7% from the average leakage current and by 6.7% from the results of simulated evolution method during standby or idle states for a set of benchmark circuits. The minimal leakage input vector, with idle input signal, can also reduce the leakage current by 6.8% from the average leakage current and by 3.2% from the results of simulated evolution method for sequential circuits.

반도체 공정의 발달로 집적도가 증가하고 문턱전압이 감소하면서, 반도체 집적회로 소모 전력에서 누설전류(leakage current)의 비중이 점차 증가하고 있다. 대기 상태에서 CMOS 조합 회로(combinational circuit)는 입력 값에 따라 누설전류가 크게 달라진다. 본 연구에서는 누설전류로 인한 소모전력을 줄이기 위해 대기 상태 (standby state) 회로의 입력 신호를 제어하며, 작은 누설전류를 갖는 입력 신호를 찾기 위한 새로운 효율적인 알고리즘을 개발하였다. 이 방법을 벤치마크 예제에 실험적으로 적용하여 누설전류 평균값에 비해 15.7%, simulated evolution 방법에 비해 6.7% 누설전류를 줄일 수 있음을 보였다. 또한 순차 회로에서도 idle 입력을 이용하여 누설전류 평균값에 비해 6.8%, simulated evolution 방법에 비해 3.2% 누설전류를 줄일 수 있었다.

Keywords

References

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