Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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ESD Failure Analysis of PMOS Transistors

PMOS 트랜지스터의 ESD 손상 분석

  • Lee, Kyoung-Su (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Jung, Go-Eun (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kwon, Kee-Won (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Chun, Jung-Hoon (School of Information and Communication Engineering, Sungkyunkwan University)
  • 이경수 (성균관대학교 정보통신공학부) ;
  • 정고은 (성균관대학교 정보통신공학부) ;
  • 권기원 (성균관대학교 정보통신공학부) ;
  • 전정훈 (성균관대학교 정보통신공학부)
  • Published : 2010.02.25
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Abstract

The studies of PMOS transistors in CMOS technologies are reviewed- focusing on the snapback and breakdown behavior of the parasitic PNP BJTs in high current regime. A new failure mechanism of PMOSFET devices under ESD conditions is also analyzed by investigating various I/O structures in a $0.13\;{\mu}m$ CMOS technology. Localized turn-on of the parasitic PNP transistor can be caused by localized charge injection from the adjacent diodes into the body of the PMOSFET, significantly degrading the ESD robustness of PMOSFETs. Based on 2-D device simulations the critical layout parameters affecting this problem are identified. Design guidelines for avoiding this new PMOSFET failure mode are also suggested.

본 논문은 미세 CMOS 공정의 PMOS 트랜지스터에 높은 전류가 인가될 때 발생하는 기생 PNP 바이폴라 트랜지스터의 스냅백과 breakdown 동작에 초점을 맞춘다. $0.13\;{\mu}m$ CMOS 공정을 이용해 제작한 다양한 I/O 구조를 분석함으로써 PMOSFET의 ESD 손상 현상의 원인을 규명하였다. 즉, 인접한 다이오드로부터 PMOSFET의 바디로 전하가 주입됨으로써 PMOSFET의 기생 PNP 트랜지스터가 부분적으로 turn-on되는 현상이 발생하여 ESD에 대한 저항성을 저하시킨다. 2차원 소자 시뮬레이션을 통해 레이아웃의 기하학적 변수의 영향을 분석하였다. 이를 기반으로 새로운 PMOSFET ESD 손상을 방지하는 설계 방법을 제안한다.

Keywords

References

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