Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of a 6bit 250MS/s CMOS A/D Converter using Input Voltage Range Detector

입력전압범위 감지회로를 이용한 6비트 250MS/s CMOS A/D 변환기 설계

  • Received : 2010.01.12
  • Published : 2010.05.25
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Abstract

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

본 논문에서는 무선통신시스템의 수신단에 적용될 수 있는 6비트 250MS/s 플래쉬 A/D 변환기를 설계하였다. 제안하는 플래쉬 A/D 변환기는 기준 저항열에 입력전압범위 감지회로를 사용하여 비교기에서 소모하는 동적소비전력을 최소화 되게 설계하였다. 기존 플래시 A/D 변환기보다 아날로그단 소비전력은 4.3% 증가한 반면에, 디지털단 소비전력은 1/7로 감소하여 전체 소비전력은 1/2 정도로 감소하였다. 설계된 A/D 변환기는$0.18{\mu}m$ CMOS 1-poly 6-metal 공정으로 제작되었으며 측정 결과 입력 범위 0.8Vpp, 1.8V의 전원 전압에서 106mW의 전력소모를 나타내었다. 250MS/s의 변환속도와 30.27MHz의 입력주파수에서 4.1비트의 유효비트수를 나타내었다.

Keywords

References

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