JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

Dynamic Reference Scheme with Improved Read Voltage Margin for Compensating Cell-position and Background-pattern Dependencies in Pure Memristor Array

  • Shin, SangHak (School of Electrical Engineering, Kookmin University) ;
  • Byeon, Sang-Don (School of Electrical Engineering, Kookmin University) ;
  • Song, Jeasang (School of Electrical Engineering, Kookmin University) ;
  • Truong, Son Ngoc (School of Electrical Engineering, Kookmin University) ;
  • Mo, Hyun-Sun (School of Electrical Engineering, Kookmin University) ;
  • Kim, Deajeong (School of Electrical Engineering, Kookmin University) ;
  • Min, Kyeong-Sik (School of Electrical Engineering, Kookmin University)
  • Received : 2015.08.28
  • Accepted : 2015.10.16
  • Published : 2015.12.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a new dynamic reference scheme is proposed to improve the read voltage margin better than the previous static reference scheme. The proposed dynamic reference scheme can be helpful in compensating not only the background pattern dependence but also the cell position dependence. The proposed dynamic reference is verified by simulating the CMOS-memristor hybrid circuit using the practical CMOS SPICE and memristor Verilog-A models. In the simulation, the percentage read voltage margin is compared between the previous static reference scheme and the new dynamic reference scheme. Assuming that the critical percentage of read voltage margin is 5%, the memristor array size with the dynamic scheme can be larger by 60%, compared to the array size with the static one. In addition, for the array size of $64{\times}64$, the interconnect resistance in the array with the dynamic scheme can be increased by 30% than the static reference one. For the array size of $128{\times}128$, the interconnect resistance with the proposed scheme can be improved by 38% than the previous static one, allowing more margin on the variation of interconnect resistance.

Keywords

References

  1. D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Wiliams, "The missing memristor found," Nature, vol. 453, pp. 80-83, 2008. https://doi.org/10.1038/nature06932
  2. E. Linn, R. Rosezin, C. Kügeler, and R. Waser "Complementary resistive switches for passive nanocrossbar memories," Nature Materials,.vol. 9, pp. 403-406, May 2010. https://doi.org/10.1038/nmat2748
  3. J. J. Yang, M. D. Pickett, X. Li, D. A. Ohlberg, D. R. Stewart, and R. S. Williams, "Memristive switching mechanism for metal/oxide/metal nanodevices," Nat. Nanotechnol., vol. 3, pp. 429- 433, Jul. 2008. https://doi.org/10.1038/nnano.2008.160
  4. S. Yu, J. Laing, Y. Wu, and H. Wong, "Read/write schemes analysis for novel complementary resistive switches in passive crossbar memory array," Nanotechnol., vol. 21, pp. 465202-1- 465202-5, Oct. 2010. https://doi.org/10.1088/0957-4484/21/46/465202
  5. R. Rosezin, El. Linn, L. Nielen, C. Kugeler, R. Bruchhaus, and R. Waser, "Integrated complementary resistive switches for passive highdensity nanocrossbar arrays," IEEE Electron Device Lett., vol. 32, no. 2, pp. 191-193, Feb. 2011. https://doi.org/10.1109/LED.2010.2090127
  6. P. F. Chiu, B. Nikolic, "A differential 2R crosspoint RRAM array with zero stanby current," IEEE Trans. Circuits Syst, vol. 62, no. 5, pp. 461- 465, May 2015. https://doi.org/10.1109/TCSII.2014.2385431
  7. S. Tappertzhofen, E. Linn, L. Nielen, R. Rosezin, F. Lentz, R. Bruchhaus, I.Valov, U.Bottger, and R.Waser, "Capacity based nondestructive readout for complementary resistive switches," Nanotechnology, vol. 22, no. 39, pp. 395203-1- 395203-7, Sep. 2011. https://doi.org/10.1088/0957-4484/22/39/395203
  8. Y. Deng, P. Huang, B. Chen, X. Yang, B. Gao, J. Wang, L. Zeng, G. Du, J. Kang, and X. Liu, "RRAM crossbar array with cell selection device: a device and circuit interaction study," IEEE Trans. Electron Devices., vol. 60, no. 2, pp. 719-726, Feb. 2013. https://doi.org/10.1109/TED.2012.2231683
  9. J. Liang and S. Philip Wong, "Cross-point memory array without cell selectors-device characteristics and data storage pattern dependencies," IEEE Trans. Electron Devices., vol. 57, no. 10, pp. 2531- 2538, Oct. 2010. https://doi.org/10.1109/TED.2010.2062187
  10. D. Lewis and H. Lee, "Architectural evaluation of 3D stacked RRAM caches," in Proc. IEEE Int. Conf. 3D Syst. Integration, 2009 pp. 1-4.
  11. C. Kugeler, M. Meier, R. Rosezin, S. Gilles, and R. Waser, "High density 3D memory architecture based on the resistive switching effect," Solid State Electron, vol 53, pp. 1287-1292, Oct. 2009. https://doi.org/10.1016/j.sse.2009.09.034
  12. E. Ou, and S. S. Wong, "Array architecture for a nonvolatile 3-dimensinal cross-point resistancechange memory," IEEE J. Solid-State Circuits, vol. 46, no. 9, pp. 2158-2170, Sep. 2011. https://doi.org/10.1109/JSSC.2011.2148430
  13. Y. C. Chen, H. Li, W. Zhang, R. E. Pino, "The 3-D stacking bipolar RRAM for high density," IEEE Trans. Nanotechnology, vol. 11, no. 5, Sep. 2012.
  14. C. H. Wang, Y. H. Tsai, K. C. Lin, M. F. Chang, Y. C. King, and C. J Lin, "Three-dimensional $4F^2$ ReRAM cell with CMOS logic compatible," in Proc. IEEE Int. Electron Device Meeting, 2010, pp. 29.6.1-29.6.4.
  15. J. Mustafa, and R. Waser, "A novel reference scheme for reading passive resistive crossbar memories," IEEE Trans. Nanotechnology, vol. 5, no. 6, pp. 687-691, Nov. 2006. https://doi.org/10.1109/TNANO.2006.885016
  16. J. Liang, S. Yeh, S. S. Wong, H. Wong, "Scaling Challenges for the cross-point resistive memory array to sub-10nm node-an interconnect perspective," in Proc. IEEE Int. 4th IMW, 2012, pp. 1-4.
  17. S. Shin, S. D. Byeon, J. Song, S. N. Truong, H. S. Mo, and K. S. Min, "A study on the improvement of the read sensing margin of memristor array," presented at the 22nd Korean Conference on Semiconductors, Incheon, Korea, Feb. 2015.
  18. Virtuoso Spectre Circuit Simulator User Guide 2004 CADENCE, San Jose, CA, USA.
  19. ITRS, International Technology Roadmap for Semiconductors, 2013.
  20. C. M. Jung, J. M. Choi, and K. S. Min, "Two-step write scheme for reducing sneak-path leakage in complementary memristor array," IEEE Trans. Nanotechnol., vol 11. No. 3, pp. 611-618, May 2012. https://doi.org/10.1109/TNANO.2012.2188302
  21. F. Corinto, A. Ascoli, "A boundary condition-based approach to the modeling of memristor nanostructures," IEEE Trans. Circuits Syst., vol. 59, no. 11, pp. 2713-2726, Nov. 2012. https://doi.org/10.1109/TCSI.2012.2190563

Cited by

  1. Spatial-Pooling Memristor Crossbar Converting Sensory Information to Sparse Distributed Representation of Cortical Neurons vol.17, pp.3, 2018, https://doi.org/10.1109/TNANO.2018.2815624