JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A 1-V 1.6-GS/s 5.58-ENOB CMOS Flash ADC using Time-Domain Comparator

  • Lee, Han-Yeol (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Jeong, Dong-Gil (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Hwang, Yu-Jeong (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Lee, Hyun-Bae (SK Hynix Semiconductor Inc.) ;
  • Jang, Young-Chan (School of Electronic Engineering, Kumoh National Institute of Technology)
  • Received : 2015.09.30
  • Accepted : 2015.10.25
  • Published : 2015.12.30
Download PDF
⟨ Previous Next ⟩

Abstract

A 1-V 1.6-GS/s 5.58-ENOB flash ADC with a high-speed time-domain comparator is proposed. The proposed time-domain comparator, which consumes low power, improves the comparison capability in high-speed operations and results in the removal of preamplifiers from the first-stage of the flash ADC. The time interpolation with two factors, implemented using the proposed time-domain comparator array and SR latch array, reduces the area and power consumption. The proposed flash ADC has been implemented using a 65-nm 1-poly 8-metal CMOS process with a 1-V supply voltage. The measured DNL and INL are 0.28 and 0.41 LSB, respectively. The SNDR is measured to be 35.37 dB at the Nyquist frequency. The FoM and chip area of the flash ADC are 0.38 pJ/c-s and $620{\times}340{\mu}m^2$, respectively.

Keywords

References

  1. M. Choi and A. A. Abidi, "A 6-b 1.3Gsample/s A/D converter in $0.35-{\mu}m$ CMOS," IEEE J. Solid-State Circuits, Vol. 36, No. 12, pp. 1847-1858, Dec. 2001. https://doi.org/10.1109/4.972135
  2. J.-I. Kim, B.-R.-S. Sung, W. Kim, and S.-T. Ryu, "A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS," IEEE J. Solid-State Circuits, Vol. 48, No. 6, pp. 1429-1441, Jun. 2013. https://doi.org/10.1109/JSSC.2013.2252516
  3. Y.-S. Shu, "A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators," IEEE Symp. VLSI Circuits, pp. 26-27, Jun. 2012.
  4. V. Hiremath and S. Ren, "A novel ultra high speed reconfigurable switching encoder for Flash ADC," Proc. The IEEE National Aerospace and Electronics Conference, pp. 320-323, July 2011.
  5. H.-Y. Lee and Y.-C. Jang, "A true single-phase clocked flip-flop witch leakage current compensation," IEICE Electronics Express, Vol. 9, No. 23, pp. 1807-1812, Dec. 2012. https://doi.org/10.1587/elex.9.1807
  6. T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, "A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture," IEEE J. Solid-State Circuits, Vol. 28, No. 4, pp. 523-527, Jun. 1993. https://doi.org/10.1109/4.210039
  7. D. Schinkel, E. Mensink, E. Klumperink, E.V. Tuijl, and B. Nauta, "Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 314-315, Feb. 2007.
  8. P. Veldhorst, G. Goksun, A.-J. Annema, B. Nauta, B. Buter, and M. Vertregt, "A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior," IEEE Proc. European Solid-State Circuits Conf., pp.464-467, Sept. 2009.
  9. K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, and T. Miki, "A 6-bit 3.5GS/s 0.9-V 98-mW flash ADC in 90 nm CMOS," IEEE J. Solid-State Circuits, Vol. 43, No. 10, pp. 2303-2310, Oct. 2008. https://doi.org/10.1109/JSSC.2008.2004326
  10. Y. Xu, L. Belostotski, and J. W. Haslett, "A 65-nm CMOS 10-GS/s 4-bit Background-Calibrated Noninterleaved Flash ADC for Radio Astronomy", IEEE Trans. VLSI, Vol. 22, No. 11, pp. 2316-2325, Nov. 2014. https://doi.org/10.1109/TVLSI.2013.2291563
  11. L. Kull, T. Toifl, M. Schmatz, P. A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T. M. Andersen, and Y. Leblebici, "A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS", in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 468-469, Feb. 2013.