IEIE Transactions on Smart Processing and Computing

대한전자공학회 (The Institute of Electronics and Information Engineers)
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Design of a G-Share Branch Predictor for EISC Processor

  • Kim, InSik (Department of Automotive Convergence, Korea University) ;
  • Jun, JaeYung (Department of Electrical and Computer Engineering, Korea University) ;
  • Na, Yeoul (Department of Electrical and Computer Engineering, Korea University) ;
  • Kim, Seon Wook (Department of Electrical and Computer Engineering, Korea University)
  • 투고 : 2015.10.12
  • 심사 : 2015.10.31
  • 발행 : 2015.10.31
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초록

This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.

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참고문헌

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