Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
권호 표지
DOI QR코드

DOI QR Code

A Study on SCR of New Structure with High Holding Voltage Characteristics by Applying Series Connected-NPN and N-Stack Technology

Series Connected-NPN 및 N-Stack기술 적용을 통하여 높은 홀딩전압특성을 갖는 새로운 구조의 SCR에 관한 연구

  • Seo, Jeong-Ju (Dept. of Electronics Engineering, DanKook University) ;
  • Kwon, Sang-Wook (Dept. of Electronics Engineering, DanKook University) ;
  • Do, Kyoung-Il (Dept. of Electronics Engineering, DanKook University) ;
  • Lee, Byung-Seok (Dept. of Electronics Engineering, DanKook University) ;
  • Koo, Yong-Seo (Dept. of Electronics Engineering, DanKook University)
  • Received : 2019.03.12
  • Accepted : 2019.03.26
  • Published : 2019.03.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, we propose a novel ESD device with improved characteristics of LVTSCR, which is a representative ESD protection device, and verify the N-stack technology for design optimized for each required voltage of a specific application. The characteristics of the holding voltage and the trigger voltage, which are the main parameters, are examined and the temperature characteristic, which is an indicator of the tolerance characteristic, is also verified. well region and a parasitic NPN to form a series-connected structure. We used synopsys' T-cad simulation tool for characterization.

본 논문에서는 대표적인 ESD 보호소자인 LVTSCR의 특성을 향상시킨 새로운 구조의 ESD소자를 제안하고 특정 application의 각 요구전압에 최적화된 설계를 위한 N-stack 기술에 대하여 검증한다. 주요 파라미터인 홀딩전압과 트리거전압에 대하여 특성을 파악하고 감내특성의 지표인 온도특성 또한 검증한다. well영역의 추가구성과 기생 npn BJT를 추가로 직렬 연결된 구조를 형성하여 보다 향상된 전기적 특성을 갖는다. 특성 검증을 위해 synopsys 사의 T-cad simulation tool을 이용하였다.

Keywords

JGGJB@_2019_v23n1_338_f0001.png 이미지

Fig. 1. Cross sectional view of LVTSCR. 그림 1. LVTSCR의 단면도

JGGJB@_2019_v23n1_338_f0002.png 이미지

Fig. 2. Equivalent circuit of LVTSCR. 그림 2. LVTSCR의 등가회로

JGGJB@_2019_v23n1_338_f0003.png 이미지

Fig. 3. Cross sectional view of Proposed Device. 그림 3. 제안된 소자의 단면도

JGGJB@_2019_v23n1_338_f0004.png 이미지

Fig. 4. Equivalent circuit of Proposed Device. 그림 4. 제안된 소자의 등가회로

JGGJB@_2019_v23n1_338_f0005.png 이미지

Fig. 5. Cross sectional view of N-stacked LVTSCR. 그림 5. N-stack 기술을 적용한 LVTSCR의 단면도

JGGJB@_2019_v23n1_338_f0006.png 이미지

Fig. 6. Cross sectional view of N-stacked Proposed Device. 그림 6. N-stack 기술을 적용한 제안된 소자의 단면도

JGGJB@_2019_v23n1_338_f0007.png 이미지

Fig. 7. IV-Curve of LVTSCR and Proposed Device. 그림 7. LVTSCR과 제안된 소자의 IV-Curve

JGGJB@_2019_v23n1_338_f0008.png 이미지

Fig. 8. HBM-4K Temperature Characteristic of LVTSCR and Proposed Device. 림 8. LVTSCR과 제안된 소자의 HBM-4K 온도 특성

JGGJB@_2019_v23n1_338_f0009.png 이미지

Fig. 9. IV-Curve of Device with N-stack technology. 그림 9. N-stack 기술이 적용된 소자의 IV-Curve

Table 1. Trigger voltage and Holding voltage measurement results for each structure. 표 1. 각 구조별 트리거전압과 홀딩전압 측정결과

JGGJB@_2019_v23n1_338_t0001.png 이미지

Table 2. HBM-4K Temperature measurement results for each structure. 표 2. 각 구조별 HBM-4K 온도측정 결과

JGGJB@_2019_v23n1_338_t0002.png 이미지

References

  1. S. Tiwari, T. Undeland, S. Basu, and W. Robbins, "Silicon carbide power transistors, characterization for smart grid applications," in Power Electronics and Motion Control Conference(EPE/PEMC), 2012 15th International, pp. LS6d.2-1-LS6d.2-8, 2012. DOI: 10.1109/EPEPEMC.2012.6397497
  2. R. Kaplar, M. J. Marinella, S. DasGupta, M. A. Smith, S. Atcitty, M. Sun, and T. Palacios, "Characterization and reliability of sic-and ganbased power transistors for renewable energy applications," in 2012 IEEE Energytech,, EOS/ESD Symp, pp. 77-86, 2012. DOI: 10.1109/EOSESD.2006.5256797
  3. T. Phulpin, D. Tremouilles, K. Isoird, D. Tournier, P. Godignon, P.Austin, "Analysis of an ESD failure mechanism on a SiC MESFET," Microelectronics Reliability, Volume 54, Issues- 10, pp. 2217-2221, 2014. DOI: 10.1016/j.microrel.2014.07.134
  4. Fayyaz A, Castellazzi A, "Performance and robustness testing of SiC power devices," In: 6th IET international conference on power electronics, machines and drives (PEMD 2012), pp. 1-5, 2012. DOI: 10.1049/cp.2012.0152
  5. Kyoung-Il Do, Byoung-Seok Lee, Yong-Seo Koo, "Study on 4H-SiC GGNMOS based ESD Protection Circuit with Low Trigger Voltage Using Gate-Body Floating Technique for 70V Application," in Electron Device Letter, vol. 40, pp. 283-286, 2018, DOI : 10.1109/LED.2018.2885846