Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
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Recent Progress of Hybrid Bonding and Packaging Technology for 3D Chip Integration

3D 칩 적층을 위한 하이브리드 본딩의 최근 기술 동향

  • Chul Hwa Jung (Dept. of Intelligence Semiconductor Engineering, University of Seoul) ;
  • Jae Pil Jung (Dept. of Materials Science and Engineering, University of Seoul)
  • 정철화 (서울시립대학교 지능형반도체학과) ;
  • 정재필 (서울시립대학교 신소재공학과)
  • Received : 2023.11.07
  • Accepted : 2023.12.12
  • Published : 2023.12.31
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Abstract

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

Keywords

Acknowledgement

이 연구는 산업통상자원부(MOTIE) 및 한국산업기술진흥원(KIAT)의 지원을 받아 수행된 연구입니다(P0018010, 2023).

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