• Title/Summary/Keyword: Offset

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Inverse Kinematic Analysis of a 6-DOF Collaborative Robot with Offset Wrist (Offset Wrist를 갖는 6자유도 협동로봇의 역기구학 해석)

  • Kim, Gi-Seong;Kim, Han-Sung
    • Journal of the Korean Society of Industry Convergence
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    • v.24 no.6_2
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    • pp.953-959
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    • 2021
  • In this paper, the numerical inverse kinematics analysis is presented for a collaborative robot with an offset wrist. Robot manipulators with offset wrist are widely used in industrial applications, due to many advantages over those with wrist center and those with three parallel axes such as simple mechanical design, light weight, and so on. There may not exist a closed-form solution for a robot manipulator with offset wrist. A simple numerical method is applied to solve the inverse kinematics with offset wrist. Singularity is analyzed using Jacobian matrix and the numerical inverse kinematics algorithm is implemented on the real-time controller.

Design of HALL effect integrated circuit with reduced wolgate offset in silicon bipolar technology (옵셋전압을 저감시킨 실리콘 바이폴라 홀 IC 설계)

  • 김정언;홍창희
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.1
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    • pp.138-145
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    • 1995
  • The offset voltage in silicon Hall plates is mainly caused by stress and strain in package, and by alignment in process. The offset voltage is appeared random for condition change with time in the factory, is non-linearly changed with temperature. In this paper proposed new method of design of Hall IC, and methematicaly proved relation layout of chip of 90$^{\circ}$-shift-current Hall plate pair is matched with "Differentail to single ended Conversion amplifier." In the experiment, the offset voltage is reduced about 1/100 time than the original offset voltage.

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Self tuning control with offset elimination for nonminimum phase system (비최소 위상 시스템에 대하여 오프셋(offset) 제거 기능을 가진 자기 동조 제어)

  • 나종래;변증남
    • 제어로봇시스템학회:학술대회논문집
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    • 1986.10a
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    • pp.78-82
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    • 1986
  • In the process control applications of self tuning control, a major concern of the control problem is to handle an offset caused by load disturbances and random steps occuring at random instance of time. Conventionally an integrator is incorperated in the forward path of the controller to eliminate such an offset. But this approach causes a difficulty if the adaptive part of the resultant controller is to be evaluated. In this paper a method of analyzing the adaptive system and improving the offset effect is suggested for a class of referance model method in the self tuning adaptive control system.

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Car-to-Car Offset Frontal Impact Modeling using Spring-Mass Model (Spring-Mass 모델을 이용한 차대차 부분정면충돌 모델링)

  • Lim, Jaemoon;Lee, Kwangwon
    • Journal of Auto-vehicle Safety Association
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    • v.8 no.2
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    • pp.11-16
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    • 2016
  • The objective of this study was to construct the spring-mass models for the car-to-car offset frontal impact crash. The SISAME software was utilized to extract the spring-mass models using the data from the offset frontal crash test. The spring-mass model of the passenger car could effectively approximate the crash characteristics for the offset frontal barrier impact and the car-to-car offset frontal impact scenarios.

차량의 제동이 교량에 미치는 영향

  • 곽종원
    • Computational Structural Engineering
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    • v.10 no.4
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    • pp.30-33
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    • 1997
  • 차량의 제동에 의한 기존의 연구는 차량의 bounce와 pitch에 의한 차량의 거동특성에 따른 고려만이 이루어져 왔으며 교량의 수직방향 offset에 의한 고려는 이루어지지 않았다. 여기서 교량의 offset이란 교량의 주형과 상판 그리고 교좌부의 중심간에 수직방향 높이의 차이를 말하며, 차량의 제동이 발생할 때 이러한 offset에 의한 추가적인 휨거동이 발생하므로 이러한 offset을 고려하여야 한다. 아울러 고속철도와 같은 중차량의 경우에는 교각의 상대적인 강성에 의한 효과도 고려되어야 할 것이다.

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The Effects of DC Offset on the Performance of Direct-Conversion Mobile Receiver in WCDMA System (WCDMA 시스템 직접변환 단말기 수신기에서 DC 오프셋에 의한 성능영향)

  • 이일규
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.15 no.7
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    • pp.730-735
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    • 2004
  • This paper describes what brings about DC offset and the impact or the DC offset on the performance or direct-conversion mobile receiver in WCDMA system. The performance degradation of $E_{b}/N_{o}$ due to the DC offset is presented through simulation result. Direct-conversion RF Transceiver which has the function of DC offset control is implemented and then applied to the WCDMA test-bed for the performance evaluation. The receiver performance degradation of $E_{c}/I_{o}$ is evaluated and analyzed by varying DC offset value. The practical test showed the minimum requirement of DC offset value to meet system performance.

DC-DC Boost Converter using Offset-Controlled Zero Current Sensor for Low Loss Thermoelectric Energy Harvesting Circuit (저 손실 열전변환 하베스팅을 위해 제로전류센서의 오프셋을 조절하는 부스트 컨버터)

  • Joo, Sunghwan;Kim, Kiryong;Jung, Dong-Hoon;Jung, Seong-Ook
    • Journal of IKEEE
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    • v.20 no.4
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    • pp.373-377
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    • 2016
  • This paper presents a low power boost converter using offset controlled Zero Current Sensor (ZCS) control for thermoelectric energy harvesting.[1] [5] Offset controlled ZCS uses adjustable pre-offset that is controled by 6bit code each connected gate of NMOS for switching. Offset controlled ZCS demonstrates an efficiency that is higher than using analog comparator ZCS and that is smaller area than using delay line ZCS. Experimentally, the offset controlled ZCS system consumes 10 times less power than analog comparator ZCS based system at similar performance.

DC offset Compensation Algorithm with Fast Response to the Grid Voltage in Single-phase Grid-connected Inverter (단상 계통 연계형 인버터의 빠른 동특성을 갖는 계통 전압 센싱 DC 오프셋 보상 알고리즘)

  • Han, Dong Yeob;Park, Jin-Hyuk;Lee, Kyo-Beum
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.64 no.7
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    • pp.1005-1011
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    • 2015
  • This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

An OFDM Frequency Offset Estimation Scheme Robust to Timing Error (시간 오차에 강인한 OFDM 주파수 옵셋 추정 기법)

  • Kim Sang-Hun;Yoon Seok-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.6C
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    • pp.623-628
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    • 2006
  • This paper addresses the frequency offset estimation problem in the presence of the timing error for OFDM systems. When the timing error exists, the correlation value used for the frequency offset estimation could be reduced significantly due to the timing error, resulting in considerable degradation in estimation performance. In this paper, using the coherence phase bandwidth (CPB) and a threshold, a novel frequency offset estimation scheme is proposed and based on which, an efficient timing error estimation scheme is also proposed for the re-estimation of the frequency offset. The performance comparison results show that the proposed frequency offset estimation scheme is not only more robust to the timing error but also has less computational complexity, as compared with the conventional schemes. It is also demonstrated by simulation that theproposed timing error estimation scheme gives a reliable estimate of the timing error.

Design and Fabrication of a Offset-PLL with DAC (DAC를 이용한 Offset-PLL 설계 및 제작)

  • Lim, Ju-Hyun;Song, Sung-Chan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.2
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    • pp.258-264
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    • 2011
  • In this paper, we designed a frequency synthesizer with a low phase noise and fast lock time and excellent spurious characteristics using the offset-PLL(Phase Locked Loop) that is used in GSM(Global System for Mobile communications). The proposed frequency synthesizer has low phase noise using three times down conversion and third offset frequency of this synthesizer is created by DDS(Direct Digital Synthesizer) to have high frequency resolution. Also, this synthesizer has fast switching speed using DAC(Digital to Analog Converter). but phase noise degraded due to DAC. we improved performance using the DAC noise filter.