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Investigation into Electrical Characteristics of Logic Circuit Consisting of Modularized Monolithic 3D Inverter Unit Cell

  • Lee, Geun Jae (ICT & Robotics Engineering and IITC, Hankyong National University) ;
  • Ahn, Tae Jun (Department of Electrical, Electronic, and Control Engineering, Hankyong National University) ;
  • Lim, Sung Kyu (School of Electrical and Computer Engineering, Georgia Institute of Technology) ;
  • Yu, Yun Seop (ICT & Robotics Engineering and IITC, Hankyong National University)
  • Received : 2021.11.05
  • Accepted : 2021.12.09
  • Published : 2022.06.30

Abstract

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

Keywords

Acknowledgement

This research was supported by the Basic Science Research Program through the NRF of Korea, funded by the Ministry of Education (NRF-2019R1A2C1085295). This study was also supported by the IDEC (EDA tool).

References

  1. H. Hua, C. Mineo, K. Schoenfliess, A. Sule, S. Melamed, and W. Davis, "Performance trend in three-dimensional integrated circuits," in Proceeding of 2006 International Interconnect Technology Conference, Burlingame: CA, pp. 45-47, 2006. DOI: 10.1109/IITC.2006.1648642.
  2. M. Vinet. M, P. Batude, C. Tabone, B. Previtali, C. LeRoyer, A. Pouydebasque, L. Clavelier, A. Valentian, O. Thomas, S. Michaud, L. Sanchez, L. Baud, A. Roman, V. Carron, F. Nemouchi, V. Mazzocchi, H. Grampeix, A. Amara, S. Deleonibus, and O. Faynot, "3D monolithic integration: Technological challenges and electrical results," Microelectronic Engineering, vol. 88, no. 4, pp. 331-335, 2011. DOI: 10.1016/j.mee.2010.10.022.
  3. P. S. Kanhaiya, Y. Stein, W. Lu, J. A. del Alamo, and M. M. Shulaker, "X3D: Heterogeneous monolithic 3D integration of "X" (Arbitrary) nanowires: Silicon, III-V, and carbon nanotubes," IEEE Transactions on Nanotechnology, vol. 18, pp. 270-273, 2019. DOI: 10.1109/TNANO.2019.2902114.
  4. J.-H. Kim, H.-M. Ji, M.-C. Nguyen, A. H.-T. Nguyen, S.-W. Kim, J.-Y. Baek, J. Kim, and R. Choi, "Low-temperature dopant activation using nanosecond ultra-violet laser annealing for monolithic 3D integration," Thin Solid Films, vol. 735, pp. 138864, 2021. DOI: 10.1016/j.tsf.2021.138864.
  5. D. K. Nayak, S. Banna, S. K. Samal, and S. K. Lim, "Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs," 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Rohnert Park, CA, USA, pp. 1-2, 2015. DOI: 10.1109/S3S.2015.7333538.
  6. C. Santos et al., "Thermal performance of CoolCubeTM monolithic and TSV-based 3D integration processes," 2016 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA, USA, pp. 1-5, 2016. DOI: 10.1109/3DIC.2016.7970007.
  7. S. Panth, S. Samal, Y. S. Yu, and S. K. Lim, "Design challenges and solutions for ultra-high-density monolithic 3D ICs," 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Millbrae, CA, USA, pp. 1-2, 2014. DOI: 10.1109/S3S.2014. 7028195.
  8. S. Lee and J. Park, "Architecture of 3D memory cell array on 3D IC," 2012 4th IEEE International Memory Workshop, Milan, Italy, pp. 1-3, 2012. DOI: 10.1109/IMW.2012.6213640.
  9. Y. Lee and S. K. Lim, "Ultrahigh density logic designs using monolithic 3-D integration," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 12, pp. 1892-1905, 2013. DOI: 10.1109/TCAD.2013.2273986.
  10. T. Naito, T. Ishida, T. Onoduka, M. Nishihgoori, T. Nakayama, Y. Ueno, Y. Ishimoto, A. Suzuki, W. Chung, R. Madurawe, S. Wu, S. Ikeda, and H. Oyamatsu, "World's first monolithic 3D-FPGA with TFT SRAM over 90 nm 9 layer Cu CMOS," in Proceeding of 2010 Symposium on VLSI Technology, Honolulu, HI, USA, pp. 219-220, 2010. DOI: 10.1109/VLSIT.2010.5556234.
  11. V. P. Hu, P. Su, and C. Chuang, "Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs," in Proceeding of 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, Canada, pp. 2106-2109, 2016. DOI: 10.1109/ISCAS.2016.7538995.
  12. Y. S. Yu and S. K. Lim, "Device coupling effects of monolithic 3D inverters," J. lnf. Commun. Converg. Eng. vol. 14, no. 1, pp. 40-44, 2016. DOI: 10.6109/jicce.2016.14.1.040.
  13. Y. S. Yu, S. Panth, and S. K. Lim, "Electrical coupling of monolithic 3-D inverters," IEEE Transactions on Electron Devices, vol. 63, no. 8, pp. 3346-3349, 2016. DOI: 10.1109/TED.2016.2578946.
  14. T. J. Ahn, B. H. Choi, S. K. Lim, and Y. S. Yu, "Electrical coupling and simulation of monolithic 3D logic circuits and static random access memory," Micromachines, vol. 10, no. 637, 2019. DOI: 10.3390/mi10100637.
  15. N. H. E. Weste and D. Harris, CMOS VLSI Design A Circuits and Systems Perspective, 3rd ed., Boston, MA: Addison-Wesley, 2005.
  16. Silvaco Int. ATLAS ver. 50. 30. 0. R Manual, 2020. Silvaco Int, Santa Clara, CA, USA.
  17. T. J. Ahn, R. Perumal, S. K. Lim, and Y. S. Yu, "Parameter extraction and power/performance analysis of monolithic 3-D Inverter (M3INV)," IEEE Transactions on Electron Devices, vol. 66, no. 2, pp. 1006-1011, 2019. DOI: 10.1109/TED.2018.2885817.
  18. HSPICE Reference Manual: MOSFET Models, Synopsys, Inc., Mountain View, CA, USA, 2016.