• Journal of Korea Multimedia Society
• /
• v.18 no.3
• /
• pp.312-322
• /
• 2015

In this paper a new defect detection method for flat panel display that does not require any separately prepared reference images and shows robustness against problems with regard to pixel tolerance and nonuniform illumination condition is proposed. In order to perform defect detection under any magnification value of camera, the proposed method automatically obtains the value of pattern interval through an image analysis. Using the information for pattern interval, an advanced PCSR-G method presented in this paper utilizes neighboring patterns as its reference images instead of utilizing any separately prepared reference images. Also this paper proposes a scheme to improve the performance of the conventional PCSR-G method by extracting and applying additional information for pixel tolerance and intensity distribution considering the value of pattern interval. Simulation results show that the performance of the proposed method utilizing pixel tolerance and intensity distribution is superior to that of the conventional method. Also, it is proved that the proposed method that is implemented using parallel technique based on GPGPU can be applied to real system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.11
• /
• pp.23-29
• /
• 2010

This paper presents a method for constructing a memory system using defective memory chips comprising faulty storage blocks. The three-dimensional memory system introduced here employs a die-stacked structure of faulty memory chips. Signals lines passing through the through-silicon-vias (TSVs) connect chips in the defect tolerant structure. Defective chips are classified into several groups each group comprising defective chips having faulty blocks at the same location. A defect tolerant memory system is constructed using chips from different groups. Defect-free storage blocks from spare chips replace faulty blocks using additional routing circuitry. The number of spare chips for defect tolerance is $s={\ulcorner}(k{\times}n)/(m-k){\urcorner}$ to make a system defect tolerant for (n+s) chips with k faulty blocks among m independently addressable blocks.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.6 no.3
• /
• pp.397-404
• /
• 2011

In this research, wish to suggest method to embody system that can accommodate defect of PLC and find actual propriety. Defect permission control system minimizes production damage because enables repair and checking without discontinuance and improve believability about whole system. Propose duplexing of system to embody this fault tolerant system. Therefore, composed control system that can permit defect or breakdown duplexings of various module proposing this system, and confirms to simulation and actuality kiln of defect permission control system through an application experiment, and compares for mean time between defect by estimate and defect special quality and system configuration of failure(failure) to improve believability of PLC control system together. In proposed system expression method and system mode and relation with operation mode, error discovery mode and switching tube of duplexing mode, and PLC's central processing unit of node study algorithm about master-standby conversion driving and continuous operation of 2 channels method that have 2 that is not one and deduced continuous operation method and result about defect permission in this algorithm and applies this result to actuality kiln control system and confirms continuous operation about PLC defect permission.

• International Journal of Aeronautical and Space Sciences
• /
• v.17 no.1
• /
• pp.109-119
• /
• 2016

When manufactured parts undergo large deformations during the manufacturing process, the global specifications of a part based on the concept of tolerance zone defined in the ISO 1101 standard [1] enable one to control the part's global defects. However, the extent of this tolerance zone is too large when the objective is to minimize local defects, such as hollows and bumps. Therefore, it is necessary to address local defects and global defects separately. This paper refers to the ISO 10579 standard [2] for flexible parts, which enables us to define a stressed state in order to measure the part by straightening it to simulate its position in the mechanism. The originality of this approach is that the straightening operation is performed numerically by calculating the displacement of a cloud of points. The results lead to a quantification of the global defects through various simple models and enable us to extract local defects. The outcome is an acceptable tolerance solution. The procedure is first developed for the simple example of a steel bar with a rectangular cross section, then applied to an industrial case involving a complex 3D surface of a turbine blade. The specification is described through ISO standards both in the free state and in the straightened state.

• Prospectives of Industrial Chemistry
• /
• v.22 no.3
• /
• pp.11-30
• /
• 2019

나노스케일 구조를 갖는 납 기반 할로겐화 페로브스카이트는 조절 가능한 방출 파장과 결함 내성(defect-tolerance)을 가지며, 높은 광 발광 양자 수율과 물질의 실온 합성 가능성으로 인해 최근 많은 관심을 받았다. 이러한 특성은 디스플레이에 적용되었을 때, 넒은 색 영역을 표현할 수 있다. 그러나 납의 독성이 페로브스카이트 디스플레이의 상용화를 방해한다. 따라서 최근에 비납계 할로겐화 페로브스카이트 나노결정에 대한 연구가 진행되었다. 본 글에서 우리는 비납계 페로브스카이트 나노결정의 설계 및 광 물리적 특성 및 발광 소자로의 응용에 대한 우리의 견해에 대하여 서술하며, 할로겐화 페로브스카이트 나노결정의 특징, 납을 대체할 수 있는 후보 원소에 대한 논의, 콜로이드성 비납계 페로브스카이트 나노결정을 합성하는 방법, 이들의 광학 특성을 제어하고 향상시키는 방법, 발광소자에서 비납계 페로브스카이트 나노결정을 사용한 최근의 연구 동향 및 이 분야에 대한 전망을 서술한다.

• Journal of KIISE:Computer Systems and Theory
• /
• v.37 no.5
• /
• pp.257-271
• /
• 2010

As the end of photolithographic integration era is approaching fast, numerous nanoscale devices and systems based on novel nanoscale materials and assembly techniques are recently emerging. Notably, various reconfigurable architectures with considerable promise have been proposed based on nanowire crossbar structure as the primitive building block. Unfortunately, high-density sys-tems consisting of nanometer-scale elements are likely to have numerous physical imperfections and variations. Therefore, defect-tolerance is considered as one of the most exigent challenges in nanowire crossbar systems. In this work, three different defect-avoidant logic mapping algorithms to circumvent defective crosspoints in nanowire reconfigurable crossbar systems are evaluated in terms of various performance metrics. Then, a novel method to find the most cost-effective repair solution is demonstrated by considering all major repair parameters and quantitatively estimating the performance and cost-effectiveness of each algorithm. Extensive parametric simulation results are reported to compare overall repair costs of the repair algorithms under consideration and to validate the cost-driven repair optimization technique.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.39 no.4
• /
• pp.423-428
• /
• 2015

To identify locations and causes of interference among parts of an indoor air-conditioning unit, a 3D tolerance analysis was performed and optimized with respect to assembly gaps and the tolerance of each part. The maximum value of the defect rate resulting from the tolerance analysis was found to be 72.6 at the assembly portion of the body and drain. The maximum displacement caused by the thermal deformation during a heating operation was calculated to be approximately 1 mm by using finite element analysis (FEA). Therefore, it is possible that an interference among the assembled parts occurs. The tolerance of the drain was modified by the results of the sensitivity analysis. As a result, the defect rate was greatly reduced to 0.03. Through the FEA results of the indoor air-conditioning unit, it was shown that the improved tolerance of the drain decreased the interference among the assembled parts even though thermal deformation occurs during operation.

• Journal of Korean Institute of Industrial Engineers
• /
• v.28 no.1
• /
• pp.57-62
• /
• 2002

The semiconductor industry has continuously been looking for the ways to improve yield and to reduce manufacturing cost. The layout modification approach, one of yield enhancement techniques, is applicable to all design styles, but it does not require any additional resources in terms of silicon area. The layout modification method for yield enhancement consists of making local variations in the layout of some layers in such a way that the critical area, and consequently the sensitivity of the layer to point defects, is reduced. Chen and Koren (1995) proposed a greedy algorithm that removes defect sensitive area using via moving, but it is easy to fall into a local minimum. In this paper, we present a via moving algorithm using simulated annealing and enhance yield by diminishing defect sensitive area. As a result, we could decrease the defect sensitive area effectively compared to the greedy algorithm presented by Chen and Koren. We expect that the proposed algorithm can make significant contributions on company profit through yield enhancement.

• Journal of the Korean Society for Nondestructive Testing
• /
• v.32 no.1
• /
• pp.56-63
• /
• 2012

In this study, a field applicability of reboiler tube was evaluated by comparing ECT signal with IRIS signal about wall loss rate and remaining wall thickness using worked austenite STS 316L ASME standard calibration tube. In the case of wall-loss rate, as a result, tolerance about $20%{\times}4$ flat bottom hole and 10% O D groove(ECT), 80% defect and 10% O D groove(IRIS) occurred up to ${\pm}15%$. In the case of remaining wall thickness, ECT was satisfied with the both tolerance, but tolerance about 80% defect occurred up to ${\pm}15%$ in IRIS. Therefore, if the IRIS is performed for interpretation of non-relevant indication and measurement of wall-loss rate after ECT, reliability is supposed to be improved.

• Journal of Korean Society for Quality Management
• /
• v.50 no.3
• /
• pp.533-543
• /
• 2022

Purpose: The purpose of this study is to identify and resolve the causes of defects in the unmanned aerial vehicle launch system(propulsion wire fracture, rear rail deformation) and to prevent recurrence. Methods: The causes of the two defects were derived through fault tree analysis for each of the two defects and fault reproduction tests. In the case of propulsion wire, the installation of a high speed camera to check the behavior of wire was the driving force behind the defect resolution. Results: The results of this study are as follows; It was determined that the thickness of the washer was less than the maximum tolerance of the pulley was the cause of the propulsion wire fracture defect. Failure to comply with the launch procedure and insufficient safety margin were judged as the cause of the rear rail deformation defect. Accordingly, the configuration was changed to remove each defect. Conclusion: The case of this study was conducted to eliminate defects in the launch system for UAV. The causes of defects were estimated through fault tree analysis. After the configuration change, Structural analysis and launch tests were performed to demonstrate the safety and effectiveness of the modified configuration. As a result, the effect of the modified configuration was verified.