Novel class A CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well standard CMOS process for high-frequency current-mode signal processing were developed. The CCII consists of a regulated current-cell for the voltage input and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated cCII show that the current input impedance is 308 .ohm. and the 3-dB cutoff frequency when used as a voltage amplifier extends beyond 10MHz. The linear dynamic ranges of voltage and current are from -0.5V to 1.5V and from -100.mu.A to +120.mu.A for supply voltage V$\_$DD/ = -V$\_$SS/=2.5V, respectively. The power dissipation is 2 mW and the active chip area is 0.2 * 0.2 [mm$\^$2/].

In this paper, we propose multiple instruction issuable multi-streaming as a processor architecture for 3D graphics processor. Multistreaming can eliminate inteferences within concurrently executing instructions inthe pipelined processor to allow enough parallelism for parallel processing. Through cycle level simulation study, we show that the proposed architecture outperforms a conventional RISC processor, MIPS R3000 by three times with reasonable resource overheads. Multiple instruction issuable multistreaming processor will be a bood architecture for instruction processor when a large number of threads are guaranteed.

This paper proposes an imprecise compuitation model for DCT considering QOS of images and a two dimensional DCT architecture for imprecise computations. In case that many processes are scheduling in a hard real time system, the system resources are shared among them. Thus all processes can not be allocated enough system resources (such as processing power and communication bandwidth). The imprecise computtion model can be used to provide scheduling flexibility and various QOS(quality of service)levels, to enhance fault tolerance, and to ensure service continuity in rela time systems. The DCT(discrete cosine transform) is known as one of popular image data compression techniques and adopted in JPEG and MPEG algorithms since the DCT can remove the spatial redundancy of 2-D image data efficiently. Even though many commercial data compression VLSI chips include the DCST hardware, the DCT computation is still a very time-consuming process and a lot of hardware resources are required for the DCT implementation. In this paper the DCT procedure is re-analyzed to fit to imprecise computation model. The test image is simulated on teh base of this model, and the computation time and the quality of restored image are studied. The row-column algorithm is used ot fit the proposed imprecise computation DCT which supports pipeline operatiions by pixel unit, various QOS levels and low speed stroage devices. The architecture has reduced I/O bandwidth which could make its implementation feasible in VLSI. The architecture is proved using a VHDL simulator in architecture level.

Fixed-point optimization utility software that can aid scaling and wordlength determination of digital signal processign algorithms written in C or C$\^$++/ language is developed. This utility consists of two programs: the range estimator and the fixed-point simulator. The former estimates the ranges of floating-point variables for automatic scaling purpose, and the latter translates floating-point programs into fixed-point equivalents for evaluating te fixed-point performance by simulation. By exploiting the operator overloading characteristics of C$\^$++/ language, the range estimation and the fixed-point simulation can be conducted just by modifying the variable declaration of the original program. This utility is easily applicable to nearly all types of digital signal processing programs including non-linear, time-varying, multi-rate, and multi-dimensional signal processing algorithms. In addition, this software can be used for comparing the fixed-point characteristics of different implementation architectures.

Processors using the superscalar rchitecture can achieve high performance by executing multipel instructions in a clock cycle. It is made possible by having multiple functional units and issuing multiple instructions to functional units simultaneously. But instructions can be dependent on one another and these dependencies prevent some instructions form being issued at the same cycle. In this paper, we designed an issue unit of a superscalar RISC microprocessor that can issue four instructions per cycle. The issue unit receives instructions form a prefetch unit, and issues them in order at a rate of as high as four instructions in one cycle for maximum utilization of functional units. By using an instruction buffer, the unit decouples instruction fetch and issue to improve instruction ussue rate. The issue unit is composed of an instruction buffer and an instruction decoder. The instruction buffer aligns and stores instructions from the prefetch unit, and sends the earliest four available isstructions to the instruction decoder. The instruction decoder decodes instructions, and issues them if they are free form data dependencies and necessary functional units and rgister file prots are available. The issue unit is described with behavioral level HDL (lhardware description language). The result of simulation using C programs shows that instruction issue rate is improved as the instruction buffer size increases, and 12-entry instruction buffer is found to be optimum considering performance and hardware cost of the instruction buffer.

In this paper, an efficient BILBO(named EBILBO) is proposed for batch testing application when a BIST (built-in self test) circuit is implemented on ASIC. In a large and complex circuit, the proposed algorithm of batch testing has one pin-count that can easily control 4 test modes in the normal speed of circuit operation. For the implementation of the BIST cifcuit, the test patern needed is generated by PRTPG(pseudo-random test pattern generator) and the ouput is observed by proposed algorithm is easily modified, such as the modelling of test pattern genration, signature EBILBO area and performance of the implemented BIST are evaluated using ISCAS89 benchmark circuits. As a resutl, in a circuit above 600 gates, it is confirmed that test patterns are genrated flexibly about 500K as EBILBO area is 59%, and the range of fault coverage is from 88.3% to 100%. And the optimized operation frequency of EBILBO designed and the area are 50MHz and 150K respectively. On the BIST circit of the proposed batch testing, the test mode of EBILBO is able to execute as realtime that has te number of s$\^$+/n$\^$+/(2s/2p-1) clocks simultaneously with the normal mode of circuit operation. Also the proposed algorithm is made of the library with VHDL coding thus, it will be widely applied to DFT (design for testability) that satisfies the design and test field.

The HMM-Net is an architecture for a neural network that implements a hidden markov model(HMM). The architecture is developed for the purpose of combining the classification power of neural networks with the time-domain modeling capability of HMMs. Criteria which are used for learning HMM_Net classifiers are maximum likelihood(ML), maximum mutual information (MMI), and minimization of mean squared error(MMSE). In this classifiers trained by the gradient descent algorithm with the above criteria. Experimental results for the isolated numbers from /young/to/koo/ show that in the binary inputs the performance of MMSE is better than the others, while in the fuzzy inputs the performance of MMI is better than the others.

This paper presents a system which recognizes dynamic hand gestures for virtual reality(VR). A dynamic hand gesture is a method of communication for a computer and human who uses gestures, especially both hands and fingers. Since the human hands and fingers are not the same in physical dimension, the same form of a gestrue produced by two persons with their hands may not have the same numerical values which are obtained through electronic sensors. In this paper, we apply a fuzzy min-max neural network and feature analysis method using fuzzy logic for on-line pattern recognition.

Based on the curve segment grouping, an efficient recognition of round objects form partially occuluded round boundaries is proposed. Curve segments are extracted from an image using a criterion based on the intra-segment curvature and local contrast. During the curve segment extraction the boundaries of pratially occluding and occuluded objects are segmented to different curve segments. The extracted segments of constant intra-segment curvature are grouped to different curve segments. The extracted segments of constant intra-segment curvature are grouped nto a round boundary by the proposed grouping algorithm using inter-segment curvature which gives the relatinships among the curve segments of the same round boundary. The 1st and the 2nd order moments are used for the parameter estimation of the best fitted ellipse with round boundary, and then recognition is perfomed based on the estimated parameters. The proposed scheme processes in segment unit and is more efficient in computational complexity and memory requirements those that of the conventional scheme which processed in pixel units. Experimental results show that the proposed technique is very efficient in recognizing the round object sfrom the real images with apples and pumpkins.

Inferring and recognizing 3D objects form a 2D occuluded image has been an important research area of computer vision. The octree model, a hierarchical volume description of 3D objects, may be utilized to generate projected images from arbitrary viewing directions, thereby providing an efficient means of the data base for 3D object recognition. We present a fast algorithm of finding the 4 pairs of feature points to estimate the viewing direction. The method is based on matching the object contour to the reference occuluded shapes of 49 viewing directions. The initially best matched viewing direction is calibrated by searching for the 4 pairs of feature points between the input image and the image projected along the estimated viewing direction. Then the input shape is recognized by matching to the projectd shape. The computational complexity of the proposed method is shown to be O(n$^{2}$) in the worst case, and that of the simple combinatorial method is O(m$^{4}$.n$^{4}$) where m and n denote the number of feature points of the 3D model object and the 2D object respectively.