• 제목/요약/키워드: Embedded Clock

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A Cost-effective 60Hz FHD LCD Using 800Mbps AiPi Technology

  • Nam, Hyoung-Sik;Oh, Kwan-Young;Kim, Seon-Ki;Kim, Nam-Deog;Kim, Sang-Soo
    • Journal of Information Display
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    • v.10 no.1
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    • pp.37-44
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    • 2009
  • AiPi technology incorporates an embedded clock and control scheme with a point-to-point bus topology, thereby having the smallest possible number of interface lines between a timing controller and column drivers. A point-to-point architecture boosts the data rate and reduces the number of interface lines, because impedance matching can be easily achieved. An embedded clock and control scheme is implemented by means of multi-level signalling, which results in a simple clock/data recovery circuitry. A 46" AiPi-based 10-bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini-LVDS. The measured maximum data rate per data pair is more than 800 Mbps.

Cost Effective 60Hz FHD LCD with 800Mbps AiPi Technology

  • Nam, Hyoung-Sik;Oh, Kwan-Young;Kim, Seon-Ki;Kim, Nam-Deog;Berkeley, Brian H.;Kim, Sang-Soo;Lee, Yong-Jae;Nakajima, Keiichi
    • 한국정보디스플레이학회:학술대회논문집
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    • pp.677-680
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    • 2008
  • AiPi technology incorporates an embedded clock and control scheme with a point-to-point bus topology, achieving the smallest possible number of interface lines between a timing controller and source drivers. A 46" AiPi-based 10-bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini-LVDS. The measured maximum data rate per one data pair is more than 800Mbps.

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이동형 시스템에서 프로세서의 전력 소모 최소화를 위한 주파수 선택 알고리즘 (A Frequency Selection Algorithm for Power Consumption Minimization of Processor in Mobile System)

  • 김재진;강진구;허화라;윤충모
    • 디지털산업정보학회논문지
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    • v.4 no.1
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    • pp.9-16
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    • 2008
  • This paper presents a frequency selection algorithm for minimization power consumption of processor in Mobile System. The proposed algorithm has processor designed low power processor using clock gating method. Clock gating method has improved the power dissipation by control main clock through the bus which is embedded clock block applying the method of clock gating. Proposed method has compared power consumption considered the dynamic power for processor, selected frequency has considered energy gain and energy consumption for designed processor. Or reduced power consumption with decreased processor speed using slack time. This technique has improved the life time of the mobile systems by clock gating method, considered energy and using slack time. As an results, the proposed algorithm reduce average power saving up to 4% comparing to not apply processor in mobile system.