• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.63-71
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• 1998

Generally, electronic packaging designer uses HSPICE SOFTWARE TOOL to validate electric characteristics of traces layout before layout traces in PCB in hundreds Mb/s high speed digital circuits. We are in need of a plated through hole (PTH) model and a connector model to use HSPICE SOFTWARE TOOL. Those models have not been perfectly defined for HSPICE simulation. In this paper, we define a PTH model and a connector model for HSPICE simulation and discuss application range for these models. Th emodels are analytic models very applicable for HSPICE simulation and are used to analyze electric characteristic of the PTH and the connector in thetraces layout in high speed digital circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.105-113
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• 2004

MRAM uses magneto-resistance material as a storage element, which stores cell data as a polarization of spin in a free magnetic layer. This magneto-resistance material has hysteresis, asteroid curve at the thermal variation, and R-V characteristics for switching the data. Therefore, a macro-model which can reproduce these characteristics is required for MRAM simulation. We propose a macro-model of TMR (Tunneling Magneto Resistance) that can reproduce all of these characteristics on HSPICE. Also we propose a novel sensing scheme, which generates reference resistance having the medium value, ( $R_{H}$+ $R_{L}$)/2, for a wide range of applied voltage and present simulation results based on the HSPICE macro-model of MTJ that we have developed.d.d.

• Journal of Korea Society of Industrial Information Systems
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• v.16 no.5
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• pp.1-8
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• 2011

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method's accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.45-52
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• 2005

This paper presents the characterization of through hole vias on printed circuit board (PCB) through the time domain and frequency domain measurements. The time domain measurement was performed on a single via using the TDR, and the model parameters were extracted by the fitting simulation using HSPICE. The frequency domain measurement was also performed by using 2 port VNA, and the model parameters were extracted by fitting simulation with ADS. Using the ABCD matrices, the do-embedding equations were derived probing in the same plane in the VNA measurement. Based on the single via characterization, the differential via characterization was also performed by using TDR measurements. The time domain measurements were performed by using the odd mode and even mode sources in TDR module, and the Parameter values were extracted by fitting with HSPICE. Comparing measurements with simulations, the maximum calculated differences were $14\%$ for single vias and $17\%$ for differential vias.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.385-388
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• 2003

In this paper, a D-Latch is replaced by a memory cell on the proposed PFD to improve response tine by reducing reset me. The PFD has been simulated using HSPICE with a Hynix 0.35um CMOS process to prove the performance improvement.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.55-63
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• 1999

A new CMOS If Package design methodology is presented, analyzing the electrical characteristics of a package and its effects on the CMOS digital circuits. An analytical investigation of the package noise effects due to the simultaneous switching of the gates within a chip, i.e., simultaneous switching noise (SSN) is performed. Then not only are novel design formula to meet electrical constraints of the Package derived, but also package design methodology based on the formula is proposed. Further, in order to demonstrate the Proposed design methodology, the design results are compared with HSPICE (a general purpose circuit simulator) simulation for $0.3\mu\textrm{m}$-based CMOS circuits. According to the proposed design procedures, it is shown that the results have excellent agreements with those of HSPICE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1558-1563
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• 2007

In this paper, phase-locked loop (PLL) of a combinational architecture consisting of an adaptive bandwidth and fractional-N is presented to improve performances and reduce the order of ${\Delta}{\Sigma}$ modulator while maintaining equivalent or better performance with fast locking. The architecture of adaptive bandwidth PLL was simulated by HSPICE using 0.35m CMOS parameters. The behavioral simulation of the proposed adaptive bandwidth fractional-N PLL with a ${\Delta}{\Sigma}$ modulator was carried out by using MatLab to determine if the architecture could achieve the objectives. The HSPICE simulation showed that this type of PLL was able to fast locking, and reduce fractional spurs about 20dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1837-1844
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• 2009

In this paper, the circuit of 2 variable ternary adder and multiplier circuit using current mode CMOS are implemented. The presented ternary adder circuit and multiplier circuit using current mode CMOS are driven the voltage levels. We show the characteristics of operation for these circuits simulated by HSpice. These circuits are simulated under $0.18{\mu}m$ CMOS standard technology, $5{\mu}A$ unit current in $0.54{\mu}m/0.18{\mu}m$ ratio of NMOS length and width, and $0.54{\mu}m/0.18{\mu}m$ ratio of PMOS length and width, and 2.5V VDD voltage, MOS model Level 47 using HSpice. The simulation results show the satisfying current characteristics. The simulation results of current mode ternary adder circuit and multiplier circuit show the propagation delay time $1.2{\mu}s$, operating speed 300KHz, and consumer power 1.08mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.37-42
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• 2007

Clock grid networks are now common in most high performance microprocessors. This paper presents a new effective modeling and simulation methodology for the clock grid using scattering parameter. It also shows the effect of wire width and grid size on the clock skew of the grid. The interconnection of the clock grid is modeled by RC passive elements. The results show that the error is within 10 % comparing to Hspice simulation results.

• Journal of the Korea Society of Computer and Information
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• v.7 no.3
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• pp.56-59
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• 2002

In this study, new serial and parallel resistor and capacitor-frequency-dependent negative resistance configurations are implemented that use one plus type four-terminal floating nullor(FTFN) and three passive components. The values of simulated elements can be orthogonally adjusted without any matching condition. High pass filter designed with this FTFN and AD844. Computer simulation was performed using the AD844 macro model by HSPICE. Simulated results agree well with theoretical values.