• Proceedings of the Korean Society for Emotion and Sensibility Conference
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• 2002.05a
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• pp.221-228
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• 2002

The NAVER is based on a cluster of low-cost personal computers. The goal of NAVER is to provide flexible, extensible, scalable and re-configurable framework for the diverse virtual environments especially for Gamsung research experiments. Personal computers are divided into three servers are according to their specific functions: Render Server, Device Server and Control Server. While Device Server contains external modules requiring event-based communication for the integration, Control Server contains external modules requiring synchronous communication every frame. And, the Render Server consists of 5 managers: Scenario Manager, Event Manger, Command Manager, Interaction Manager and Sync Manager. In this paper, we discuss NAVER as effective distributed system and its application to Gamsung experiment.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.767-769
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• 2002

A novel RE configurable device composed by bare-chip, bumps and board are proposed. We call this "Field-Programmable RF Gate Array (FPRA)," This device, a kind of programmable system packages, has a potential to be applied to wireless communication terminals such as software-defined radio.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.43.6-43
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• 2002

$\textbullet$ KAEROT/m1 with an omni-directional planetary wheel mechanism for the narrow corridor. $\textbullet$ KAEROT/m2 can pass over the ditch with specially designed four wheel of a re-configurable crawler. $\textbullet$ Stereo imaging system with master manipulator enhancing the tele-presence. $\textbullet$ Small hybrid dosimeter detecting radiation dose and dose rate simultaneously.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.924-927
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• 2002

In this paper we proposed the design space exploration environment of re-configurable hybrid systems and evaluate the performance by changing design parameters. With this, we analyzed the effect of various scheduling methods which determine how we allocate hardware/software resources to application program. A simple static (fixed) mapping strategy produces almost the same performance compared with a sophisticated dynamic mapping strategy especially when a CPU is already busy with its pre-assigned own tasks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9B
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• pp.760-773
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• 2003

The Internet is evolving from best-effort service toward an integrated or differentiated service framework with quality-of-service (QoS) assurances that are required for new multimedia service applications. Given this increasing demand for high bandwidth Internet with QoS assurances in the coming years, an IP/MPLS-based control plane combined. with a wavelength-routed dense-wavelength division multiplexing (DWDM) optical network is seen as a very promising approach for the realization of future re-configurable transport networks. This paper proposes a differentiated lambda establishment process for QoS guarantees based on the differentiated MPLS service (DMS) model. According to the QoS characteristics of wavelength in optical links and the type of used Optical Cross-Connect (OXC) nodes in DWDM next generation optical Internet backbone network, a differentiated wavelength assignment strategy that considers QoS recovery capability is also suggested.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.936-939
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• 2002

FPCA is the necessary device to design of hardware at present, it is researched on many ways of applying to design caused by expansion of capacity in recent years. One of these applying ways is SoC (System on a Chip) that is proposed for realizing the basic function of a system. For realizing SoC efficiently, IP (Intellectual property) is very important and developed for re-use of hardware. A MPU for built-in exists as an IP. But almost of MPUs at present as an IPs are lengthy and large-scale for using embedded-application. Furthermore, the function of executing specific treatment critically is required to embedded MPU. We propose a flexible and small scale MPU and its design method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.67-74
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• 2005

Crypto-systems have difficulties in designing hardware due to the various standards. We propose a programmable and configurable architecture for cryptography coprocessors to accommodate various crypto-systems. The proposed architecture has a 32 bit I/O interface and internal bus width, and consists of a programmable finite field arithmetic unit, an input/output unit, a register file, and a control unit. The crypto-system is determined by the micro-codes in memory of the control unit, and is configured by programming the micro-codes. The coprocessor has a modular structure so that the arithmetic unit can be replaced if a substitute has an appropriate 32 bit I/O interface. It can be used in many crypto-systems by re-programming the micro-codes for corresponding crypto-system or by replacing operation units. We implement an elliptic curve crypto-processor using the proposed architecture and compare it with other crypto-processors

• Journal of the Optical Society of Korea
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• v.7 no.1
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• pp.28-33
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• 2003

We describe the optimal design and the fabrication of a 2$\times$2 port optical device based on the thin film filter (TFF), and also propose a 4-channel OADM module using these devices. The optical performance of the proposed OADM module is evaluated theoretically and experimentally, and is compared to that of typical OADM modules using 1$\times$2 port optical devices for 4, 8, 16 and 32 drop channels in optical transmission systems. Since the 2$\times$2 port optical device accomplishes the function of wavelength multiplexing and demultiplexing simultaneously in the proposed OADM module, the insertion loss of through channels can be improved by 1.2 dB compare to that of typical OADM modules using 1$\times$2 port optical devices. In addition, both the size and the price of the module can be reduced to 40~50%.

• Journal of Positioning, Navigation, and Timing
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• v.13 no.2
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• pp.149-158
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• 2024

Global Navigation Satellite System (GNSS) receivers are becoming increasingly sophisticated, equipped with advanced features and precise specifications, thus demanding efficient and high-performance hardware platforms. This paper presents the design and implementation of a Field-Programmable Gate Array (FPGA)-based GNSS receiver development platform for multi-band signal processing. This platform utilizes a FPGA to provide a flexible and re-configurable hardware environment, enabling real-time signal processing, position determination, and handling of large-scale data. Integrated signal processing of L/S bands enhances the performance and functionality of GNSS receivers. Key components such as the RF frontend, signal processing modules, and power management are designed to ensure optimal signal reception and processing, supporting multiple GNSS. The developed hardware platform enables real-time signal processing and position determination, supporting multiple GNSS systems, thereby contributing to the advancement of GNSS development and research.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.60-68
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• 2008

This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.