For frame synchronization in synchronous multiplexer based on SDH (Synchronous Digital Hierarchy), pointer justification mechanism (opinter adjustment) to compensate small frequency differences between the received uline clock and local clock is sed. But these pointer adjustment will introduce jitter onto tributary signal. This paper presents the bit leaking method to reduce those jitter to a level compatible with existing specification, where the simulation shows that this method reduces pointer adjustment jitter.

The cylindrical TEM mode solution for electromagnetic coupling to an angled two-wire transmission line is corrected by imposing some physical constraints additionally. The validity of the correction process is assured by showing that the corrected solution approaches the numerical result for the equivalent model of cascaded piecewise uniform sections.

A newly advanced method of characterizing large signal S-parameters of TR using the overall gain of normally operating TR is proposed based on the load pull method which gives the matching network only. Large signal S-parameters of TR are characterized from the circuit which consists of TR and 3dB Coupler Tuners at the input and output ports, and which is B class biased with 0dBminput signal. Amplifier can be designed to have 8.5dB gain at 770MHz using the calculated large signal S-parameters with the resulting gain of 8.786dB.

In this paper, the ultrasonic transducer with a spherical liquid lens is designed and an efficient method to calculate the acoustic field radiated from the transducer is presented. A prototype ultrasonic transducer with a spherical liquid lens is constructed and tested. The experimental results are compared with those of the computer simulations and good agreements are achieved. The dynamic control of the geometric focus is obtained by adjusting the radius of curvature of the lens membrane with the volumetric control of the liquid in the lens.

A guided-wave TE to TM mode converter was demonstrated by using of the off-diagonal electrooptic coefficients in LiTaO$_{3}$. The input mode is coupled to the other orthogonal mode by the electrooptically induced off-diagonal polarizability. Compared with LiNbO$_{3}$, LiTaO$_{3}$ provides a smaller birefringence and thus a larger phase match period and larger optical bnadwidth. A novel electrode structure allowed a first-order Bragg-coupling phase matching. TE/TM mode conversion efficiency of 90% at 25 [V] was demonstrated with ${\lambda}$=0.63$\mu$m He-Ne laser.

The n-channel MOSFETs with gate-$n^{-}$S/D overlapped structure have been fabricated by ITLDD(inverse-T gate lightly doped drain) technology. The gate length(L$_{mask}$) was 0.8$\mu$m. The degradation effects of hot carriers injected into the gate oxide were analyzed in terms of threshold voltage, transconductance and drain current variations. The degradation dependences on the gate voltage and drain voltage were characterized. The devices with higher n-concentration showed higher resistivity against the hot carrier injection. As the results of investigating the lifetime of the device, the lifetime showed longer than 10 years at V$_{d}$ = 5V for the overlapped devices with the implantation of an phosphorus dose of 5$\times$10$^{13}$ cm$^{-2}$ and an energy of 80 keV in the n$^{-}$resion.

The estimation of yield for semiconductor devices requires not only establishment of critical area but also a new parameter of process defect density that contains inspection mean defect density related cleanness of manufacure process line, minimum feature size and the total number of mask process. We estimate the repaired yield of memory devide, leads the semiconductor technique, repaired by redundancy scheme in relation with defect density distribution function, and we confirm the repaired yield for different devices as this model. This shows the possibility of the yield estimation as statistical analysis for the condition of device related cleanness of manufacture process line, design and manufacture process.

Device degradations by the Fowler-Nordheim tunneling have been studide. The changes of device characteristics such as the threshold voltage, subthreshold slope, I-.or. curves have been measured after bidirectionally stressing n-channel MOSFET's and p-channel MOSFET's. Also the interface states have been directly measured by the charge pumping methodIt is shown that the change of interface states is determined by the number of hole carriers tunneling the gate oxide and electrons which are trapped in the gate oxide. Also, in this paper, we propose a model for device lifetime limited by the increase of interface states.

As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.

This paper describes the design of a technology-independent logic, function, and timing extraction system from SPICE-like network descriptions. Technology-independent extraction mechanism is provided in the form of technology files containing the rules for constructing logic gates and functional blocks. The designed system can be more effectively used in cell-based design by describing the cells to be extracted. Timing extraction is performed by using a linear RC gate delay model which takes interconnection delay into account. Experimental results show that estimated delay is within 10 percents for logic gate circuits when compared with SPICE. Through higher-level design descriptions obtained by extraction, design cycles can be considerably reduces.